drivers/scsi/aic7xxx/aic7xxx_93cx6.c

   1 /*
   2  * Interface for the 93C66/56/46/26/06 serial eeprom parts.
   3  *
   4  * Copyright (c) 1995, 1996 Daniel M. Eischen
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. The name of the author may not be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * Alternatively, this software may be distributed under the terms of the
  17  * GNU General Public License ("GPL").
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  23  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  *
  31  * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.c#19 $
  32  */
  33
  34 /*
  35  *   The instruction set of the 93C66/56/46/26/06 chips are as follows:
  36  *
  37  *               Start  OP          *
  38  *     Function   Bit  Code  Address**  Data     Description
  39  *     -------------------------------------------------------------------
  40  *     READ        1    10   A5 - A0             Reads data stored in memory,
  41  *                                               starting at specified address
  42  *     EWEN        1    00   11XXXX              Write enable must precede
  43  *                                               all programming modes
  44  *     ERASE       1    11   A5 - A0             Erase register A5A4A3A2A1A0
  45  *     WRITE       1    01   A5 - A0   D15 - D0  Writes register
  46  *     ERAL        1    00   10XXXX              Erase all registers
  47  *     WRAL        1    00   01XXXX    D15 - D0  Writes to all registers
  48  *     EWDS        1    00   00XXXX              Disables all programming
  49  *                                               instructions
  50  *     *Note: A value of X for address is a don't care condition.
  51  *    **Note: There are 8 address bits for the 93C56/66 chips unlike
  52  *            the 93C46/26/06 chips which have 6 address bits.
  53  *
  54  *   The 93C46 has a four wire interface: clock, chip select, data in, and
  55  *   data out.  In order to perform one of the above functions, you need
  56  *   to enable the chip select for a clock period (typically a minimum of
  57  *   1 usec, with the clock high and low a minimum of 750 and 250 nsec
  58  *   respectively).  While the chip select remains high, you can clock in
  59  *   the instructions (above) starting with the start bit, followed by the
  60  *   OP code, Address, and Data (if needed).  For the READ instruction, the
  61  *   requested 16-bit register contents is read from the data out line but
  62  *   is preceded by an initial zero (leading 0, followed by 16-bits, MSB
  63  *   first).  The clock cycling from low to high initiates the next data
  64  *   bit to be sent from the chip.
  65  */
  66
  67 #ifdef __linux__
  68 #include "aic7xxx_osm.h"
  69 #include "aic7xxx_inline.h"
  70 #include "aic7xxx_93cx6.h"
  71 #else
  72 #include <dev/aic7xxx/aic7xxx_osm.h>
  73 #include <dev/aic7xxx/aic7xxx_inline.h>
  74 #include <dev/aic7xxx/aic7xxx_93cx6.h>
  75 #endif
  76
  77 /*
  78  * Right now, we only have to read the SEEPROM.  But we make it easier to
  79  * add other 93Cx6 functions.
  80  */
  81 struct seeprom_cmd {
  82         uint8_t len;
  83         uint8_t bits[11];
  84 };
  85
  86 /* Short opcodes for the c46 */
  87 static const struct seeprom_cmd seeprom_ewen = {9, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
  88 static const struct seeprom_cmd seeprom_ewds = {9, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
  89
  90 /* Long opcodes for the C56/C66 */
  91 static const struct seeprom_cmd seeprom_long_ewen = {11, {1, 0, 0, 1, 1, 0, 0, 0, 0}};
  92 static const struct seeprom_cmd seeprom_long_ewds = {11, {1, 0, 0, 0, 0, 0, 0, 0, 0}};
  93
  94 /* Common opcodes */
  95 static const struct seeprom_cmd seeprom_write = {3, {1, 0, 1}};
  96 static const struct seeprom_cmd seeprom_read  = {3, {1, 1, 0}};
  97
  98 /*
  99  * Wait for the SEERDY to go high; about 800 ns.
 100  */
 101 #define CLOCK_PULSE(sd, rdy)                            \
 102         while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) {   \
 103                 ;  /* Do nothing */                     \
 104         }                                               \
 105         (void)SEEPROM_INB(sd);  /* Clear clock */
 106
 107 /*
 108  * Send a START condition and the given command
 109  */
 110 static void
 111 send_seeprom_cmd(struct seeprom_descriptor *sd, const struct seeprom_cmd *cmd)
 112 {
 113         uint8_t temp;
 114         int i = 0;
 115
 116         /* Send chip select for one clock cycle. */
 117         temp = sd->sd_MS ^ sd->sd_CS;
 118         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
 119         CLOCK_PULSE(sd, sd->sd_RDY);
 120
 121         for (i = 0; i < cmd->len; i++) {
 122                 if (cmd->bits[i] != 0)
 123                         temp ^= sd->sd_DO;
 124                 SEEPROM_OUTB(sd, temp);
 125                 CLOCK_PULSE(sd, sd->sd_RDY);
 126                 SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
 127                 CLOCK_PULSE(sd, sd->sd_RDY);
 128                 if (cmd->bits[i] != 0)
 129                         temp ^= sd->sd_DO;
 130         }
 131 }
 132
 133 /*
 134  * Clear CS put the chip in the reset state, where it can wait for new commands.
 135  */
 136 static void
 137 reset_seeprom(struct seeprom_descriptor *sd)
 138 {
 139         uint8_t temp;
 140
 141         temp = sd->sd_MS;
 142         SEEPROM_OUTB(sd, temp);
 143         CLOCK_PULSE(sd, sd->sd_RDY);
 144         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
 145         CLOCK_PULSE(sd, sd->sd_RDY);
 146         SEEPROM_OUTB(sd, temp);
 147         CLOCK_PULSE(sd, sd->sd_RDY);
 148 }
 149
 150 /*
 151  * Read the serial EEPROM and returns 1 if successful and 0 if
 152  * not successful.
 153  */
 154 int
 155 ahc_read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
 156                  u_int start_addr, u_int count)
 157 {
 158         int i = 0;
 159         u_int k = 0;
 160         uint16_t v;
 161         uint8_t temp;
 162
 163         /*
 164          * Read the requested registers of the seeprom.  The loop
 165          * will range from 0 to count-1.
 166          */
 167         for (k = start_addr; k < count + start_addr; k++) {
 168                 /*
 169                  * Now we're ready to send the read command followed by the
 170                  * address of the 16-bit register we want to read.
 171                  */
 172                 send_seeprom_cmd(sd, &seeprom_read);
 173
 174                 /* Send the 6 or 8 bit address (MSB first, LSB last). */
 175                 temp = sd->sd_MS ^ sd->sd_CS;
 176                 for (i = (sd->sd_chip - 1); i >= 0; i--) {
 177                         if ((k & (1 << i)) != 0)
 178                                 temp ^= sd->sd_DO;
 179                         SEEPROM_OUTB(sd, temp);
 180                         CLOCK_PULSE(sd, sd->sd_RDY);
 181                         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
 182                         CLOCK_PULSE(sd, sd->sd_RDY);
 183                         if ((k & (1 << i)) != 0)
 184                                 temp ^= sd->sd_DO;
 185                 }
 186
 187                 /*
 188                  * Now read the 16 bit register.  An initial 0 precedes the
 189                  * register contents which begins with bit 15 (MSB) and ends
 190                  * with bit 0 (LSB).  The initial 0 will be shifted off the
 191                  * top of our word as we let the loop run from 0 to 16.
 192                  */
 193                 v = 0;
 194                 for (i = 16; i >= 0; i--) {
 195                         SEEPROM_OUTB(sd, temp);
 196                         CLOCK_PULSE(sd, sd->sd_RDY);
 197                         v <<= 1;
 198                         if (SEEPROM_DATA_INB(sd) & sd->sd_DI)
 199                                 v |= 1;
 200                         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
 201                         CLOCK_PULSE(sd, sd->sd_RDY);
 202                 }
 203
 204                 buf[k - start_addr] = v;
 205
 206                 /* Reset the chip select for the next command cycle. */
 207                 reset_seeprom(sd);
 208         }
 209 #ifdef AHC_DUMP_EEPROM
 210         printk("\nSerial EEPROM:\n\t");
 211         for (k = 0; k < count; k = k + 1) {
 212                 if (((k % 8) == 0) && (k != 0)) {
 213                         printk(KERN_CONT "\n\t");
 214                 }
 215                 printk(KERN_CONT " 0x%x", buf[k]);
 216         }
 217         printk(KERN_CONT "\n");
 218 #endif
 219         return (1);
 220 }
 221
 222 /*
 223  * Write the serial EEPROM and return 1 if successful and 0 if
 224  * not successful.
 225  */
 226 int
 227 ahc_write_seeprom(struct seeprom_descriptor *sd, uint16_t *buf,
 228                   u_int start_addr, u_int count)
 229 {
 230         const struct seeprom_cmd *ewen, *ewds;
 231         uint16_t v;
 232         uint8_t temp;
 233         int i, k;
 234
 235         /* Place the chip into write-enable mode */
 236         if (sd->sd_chip == C46) {
 237                 ewen = &seeprom_ewen;
 238                 ewds = &seeprom_ewds;
 239         } else if (sd->sd_chip == C56_66) {
 240                 ewen = &seeprom_long_ewen;
 241                 ewds = &seeprom_long_ewds;
 242         } else {
 243                 printk("ahc_write_seeprom: unsupported seeprom type %d\n",
 244                        sd->sd_chip);
 245                 return (0);
 246         }
 247
 248         send_seeprom_cmd(sd, ewen);
 249         reset_seeprom(sd);
 250
 251         /* Write all requested data out to the seeprom. */
 252         temp = sd->sd_MS ^ sd->sd_CS;
 253         for (k = start_addr; k < count + start_addr; k++) {
 254                 /* Send the write command */
 255                 send_seeprom_cmd(sd, &seeprom_write);
 256
 257                 /* Send the 6 or 8 bit address (MSB first). */
 258                 for (i = (sd->sd_chip - 1); i >= 0; i--) {
 259                         if ((k & (1 << i)) != 0)
 260                                 temp ^= sd->sd_DO;
 261                         SEEPROM_OUTB(sd, temp);
 262                         CLOCK_PULSE(sd, sd->sd_RDY);
 263                         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
 264                         CLOCK_PULSE(sd, sd->sd_RDY);
 265                         if ((k & (1 << i)) != 0)
 266                                 temp ^= sd->sd_DO;
 267                 }
 268
 269                 /* Write the 16 bit value, MSB first */
 270                 v = buf[k - start_addr];
 271                 for (i = 15; i >= 0; i--) {
 272                         if ((v & (1 << i)) != 0)
 273                                 temp ^= sd->sd_DO;
 274                         SEEPROM_OUTB(sd, temp);
 275                         CLOCK_PULSE(sd, sd->sd_RDY);
 276                         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
 277                         CLOCK_PULSE(sd, sd->sd_RDY);
 278                         if ((v & (1 << i)) != 0)
 279                                 temp ^= sd->sd_DO;
 280                 }
 281
 282                 /* Wait for the chip to complete the write */
 283                 temp = sd->sd_MS;
 284                 SEEPROM_OUTB(sd, temp);
 285                 CLOCK_PULSE(sd, sd->sd_RDY);
 286                 temp = sd->sd_MS ^ sd->sd_CS;
 287                 do {
 288                         SEEPROM_OUTB(sd, temp);
 289                         CLOCK_PULSE(sd, sd->sd_RDY);
 290                         SEEPROM_OUTB(sd, temp ^ sd->sd_CK);
 291                         CLOCK_PULSE(sd, sd->sd_RDY);
 292                 } while ((SEEPROM_DATA_INB(sd) & sd->sd_DI) == 0);
 293
 294                 reset_seeprom(sd);
 295         }
 296
 297         /* Put the chip back into write-protect mode */
 298         send_seeprom_cmd(sd, ewds);
 299         reset_seeprom(sd);
 300
 301         return (1);
 302 }
 303
 304 int
 305 ahc_verify_cksum(struct seeprom_config *sc)
 306 {
 307         int i;
 308         int maxaddr;
 309         uint32_t checksum;
 310         uint16_t *scarray;
 311
 312         maxaddr = (sizeof(*sc)/2) - 1;
 313         checksum = 0;
 314         scarray = (uint16_t *)sc;
 315
 316         for (i = 0; i < maxaddr; i++)
 317                 checksum = checksum + scarray[i];
 318         if (checksum == 0
 319          || (checksum & 0xFFFF) != sc->checksum) {
 320                 return (0);
 321         } else {
 322                 return(1);
 323         }
 324 }