powerpc/eeh: Fix PE#0 check in eeh_add_to_parent_pe()
[linux/fpc-iii.git] / drivers / net / ethernet / micrel / ks8851.h
blob852256ef1f2233b9d60efa0b01da45e128514a14
1 /* drivers/net/ethernet/micrel/ks8851.h
3 * Copyright 2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * KS8851 register definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #define KS_CCR 0x08
14 #define CCR_EEPROM (1 << 9)
15 #define CCR_SPI (1 << 8)
16 #define CCR_32PIN (1 << 0)
18 /* MAC address registers */
19 #define KS_MAR(_m) (0x15 - (_m))
20 #define KS_MARL 0x10
21 #define KS_MARM 0x12
22 #define KS_MARH 0x14
24 #define KS_OBCR 0x20
25 #define OBCR_ODS_16mA (1 << 6)
27 #define KS_EEPCR 0x22
28 #define EEPCR_EESRWA (1 << 5)
29 #define EEPCR_EESA (1 << 4)
30 #define EEPCR_EESB (1 << 3)
31 #define EEPCR_EEDO (1 << 2)
32 #define EEPCR_EESCK (1 << 1)
33 #define EEPCR_EECS (1 << 0)
35 #define KS_MBIR 0x24
36 #define MBIR_TXMBF (1 << 12)
37 #define MBIR_TXMBFA (1 << 11)
38 #define MBIR_RXMBF (1 << 4)
39 #define MBIR_RXMBFA (1 << 3)
41 #define KS_GRR 0x26
42 #define GRR_QMU (1 << 1)
43 #define GRR_GSR (1 << 0)
45 #define KS_WFCR 0x2A
46 #define WFCR_MPRXE (1 << 7)
47 #define WFCR_WF3E (1 << 3)
48 #define WFCR_WF2E (1 << 2)
49 #define WFCR_WF1E (1 << 1)
50 #define WFCR_WF0E (1 << 0)
52 #define KS_WF0CRC0 0x30
53 #define KS_WF0CRC1 0x32
54 #define KS_WF0BM0 0x34
55 #define KS_WF0BM1 0x36
56 #define KS_WF0BM2 0x38
57 #define KS_WF0BM3 0x3A
59 #define KS_WF1CRC0 0x40
60 #define KS_WF1CRC1 0x42
61 #define KS_WF1BM0 0x44
62 #define KS_WF1BM1 0x46
63 #define KS_WF1BM2 0x48
64 #define KS_WF1BM3 0x4A
66 #define KS_WF2CRC0 0x50
67 #define KS_WF2CRC1 0x52
68 #define KS_WF2BM0 0x54
69 #define KS_WF2BM1 0x56
70 #define KS_WF2BM2 0x58
71 #define KS_WF2BM3 0x5A
73 #define KS_WF3CRC0 0x60
74 #define KS_WF3CRC1 0x62
75 #define KS_WF3BM0 0x64
76 #define KS_WF3BM1 0x66
77 #define KS_WF3BM2 0x68
78 #define KS_WF3BM3 0x6A
80 #define KS_TXCR 0x70
81 #define TXCR_TCGICMP (1 << 8)
82 #define TXCR_TCGUDP (1 << 7)
83 #define TXCR_TCGTCP (1 << 6)
84 #define TXCR_TCGIP (1 << 5)
85 #define TXCR_FTXQ (1 << 4)
86 #define TXCR_TXFCE (1 << 3)
87 #define TXCR_TXPE (1 << 2)
88 #define TXCR_TXCRC (1 << 1)
89 #define TXCR_TXE (1 << 0)
91 #define KS_TXSR 0x72
92 #define TXSR_TXLC (1 << 13)
93 #define TXSR_TXMC (1 << 12)
94 #define TXSR_TXFID_MASK (0x3f << 0)
95 #define TXSR_TXFID_SHIFT (0)
96 #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
98 #define KS_RXCR1 0x74
99 #define RXCR1_FRXQ (1 << 15)
100 #define RXCR1_RXUDPFCC (1 << 14)
101 #define RXCR1_RXTCPFCC (1 << 13)
102 #define RXCR1_RXIPFCC (1 << 12)
103 #define RXCR1_RXPAFMA (1 << 11)
104 #define RXCR1_RXFCE (1 << 10)
105 #define RXCR1_RXEFE (1 << 9)
106 #define RXCR1_RXMAFMA (1 << 8)
107 #define RXCR1_RXBE (1 << 7)
108 #define RXCR1_RXME (1 << 6)
109 #define RXCR1_RXUE (1 << 5)
110 #define RXCR1_RXAE (1 << 4)
111 #define RXCR1_RXINVF (1 << 1)
112 #define RXCR1_RXE (1 << 0)
114 #define KS_RXCR2 0x76
115 #define RXCR2_SRDBL_MASK (0x7 << 5)
116 #define RXCR2_SRDBL_SHIFT (5)
117 #define RXCR2_SRDBL_4B (0x0 << 5)
118 #define RXCR2_SRDBL_8B (0x1 << 5)
119 #define RXCR2_SRDBL_16B (0x2 << 5)
120 #define RXCR2_SRDBL_32B (0x3 << 5)
121 #define RXCR2_SRDBL_FRAME (0x4 << 5)
122 #define RXCR2_IUFFP (1 << 4)
123 #define RXCR2_RXIUFCEZ (1 << 3)
124 #define RXCR2_UDPLFE (1 << 2)
125 #define RXCR2_RXICMPFCC (1 << 1)
126 #define RXCR2_RXSAF (1 << 0)
128 #define KS_TXMIR 0x78
130 #define KS_RXFHSR 0x7C
131 #define RXFSHR_RXFV (1 << 15)
132 #define RXFSHR_RXICMPFCS (1 << 13)
133 #define RXFSHR_RXIPFCS (1 << 12)
134 #define RXFSHR_RXTCPFCS (1 << 11)
135 #define RXFSHR_RXUDPFCS (1 << 10)
136 #define RXFSHR_RXBF (1 << 7)
137 #define RXFSHR_RXMF (1 << 6)
138 #define RXFSHR_RXUF (1 << 5)
139 #define RXFSHR_RXMR (1 << 4)
140 #define RXFSHR_RXFT (1 << 3)
141 #define RXFSHR_RXFTL (1 << 2)
142 #define RXFSHR_RXRF (1 << 1)
143 #define RXFSHR_RXCE (1 << 0)
145 #define KS_RXFHBCR 0x7E
146 #define KS_TXQCR 0x80
147 #define TXQCR_AETFE (1 << 2)
148 #define TXQCR_TXQMAM (1 << 1)
149 #define TXQCR_METFE (1 << 0)
151 #define KS_RXQCR 0x82
152 #define RXQCR_RXDTTS (1 << 12)
153 #define RXQCR_RXDBCTS (1 << 11)
154 #define RXQCR_RXFCTS (1 << 10)
155 #define RXQCR_RXIPHTOE (1 << 9)
156 #define RXQCR_RXDTTE (1 << 7)
157 #define RXQCR_RXDBCTE (1 << 6)
158 #define RXQCR_RXFCTE (1 << 5)
159 #define RXQCR_ADRFE (1 << 4)
160 #define RXQCR_SDA (1 << 3)
161 #define RXQCR_RRXEF (1 << 0)
163 #define KS_TXFDPR 0x84
164 #define TXFDPR_TXFPAI (1 << 14)
165 #define TXFDPR_TXFP_MASK (0x7ff << 0)
166 #define TXFDPR_TXFP_SHIFT (0)
168 #define KS_RXFDPR 0x86
169 #define RXFDPR_RXFPAI (1 << 14)
171 #define KS_RXDTTR 0x8C
172 #define KS_RXDBCTR 0x8E
174 #define KS_IER 0x90
175 #define KS_ISR 0x92
176 #define IRQ_LCI (1 << 15)
177 #define IRQ_TXI (1 << 14)
178 #define IRQ_RXI (1 << 13)
179 #define IRQ_RXOI (1 << 11)
180 #define IRQ_TXPSI (1 << 9)
181 #define IRQ_RXPSI (1 << 8)
182 #define IRQ_TXSAI (1 << 6)
183 #define IRQ_RXWFDI (1 << 5)
184 #define IRQ_RXMPDI (1 << 4)
185 #define IRQ_LDI (1 << 3)
186 #define IRQ_EDI (1 << 2)
187 #define IRQ_SPIBEI (1 << 1)
188 #define IRQ_DEDI (1 << 0)
190 #define KS_RXFCTR 0x9C
191 #define KS_RXFC 0x9D
192 #define RXFCTR_RXFC_MASK (0xff << 8)
193 #define RXFCTR_RXFC_SHIFT (8)
194 #define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
195 #define RXFCTR_RXFCT_MASK (0xff << 0)
196 #define RXFCTR_RXFCT_SHIFT (0)
198 #define KS_TXNTFSR 0x9E
200 #define KS_MAHTR0 0xA0
201 #define KS_MAHTR1 0xA2
202 #define KS_MAHTR2 0xA4
203 #define KS_MAHTR3 0xA6
205 #define KS_FCLWR 0xB0
206 #define KS_FCHWR 0xB2
207 #define KS_FCOWR 0xB4
209 #define KS_CIDER 0xC0
210 #define CIDER_ID 0x8870
211 #define CIDER_REV_MASK (0x7 << 1)
212 #define CIDER_REV_SHIFT (1)
213 #define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
215 #define KS_CGCR 0xC6
217 #define KS_IACR 0xC8
218 #define IACR_RDEN (1 << 12)
219 #define IACR_TSEL_MASK (0x3 << 10)
220 #define IACR_TSEL_SHIFT (10)
221 #define IACR_TSEL_MIB (0x3 << 10)
222 #define IACR_ADDR_MASK (0x1f << 0)
223 #define IACR_ADDR_SHIFT (0)
225 #define KS_IADLR 0xD0
226 #define KS_IAHDR 0xD2
228 #define KS_PMECR 0xD4
229 #define PMECR_PME_DELAY (1 << 14)
230 #define PMECR_PME_POL (1 << 12)
231 #define PMECR_WOL_WAKEUP (1 << 11)
232 #define PMECR_WOL_MAGICPKT (1 << 10)
233 #define PMECR_WOL_LINKUP (1 << 9)
234 #define PMECR_WOL_ENERGY (1 << 8)
235 #define PMECR_AUTO_WAKE_EN (1 << 7)
236 #define PMECR_WAKEUP_NORMAL (1 << 6)
237 #define PMECR_WKEVT_MASK (0xf << 2)
238 #define PMECR_WKEVT_SHIFT (2)
239 #define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
240 #define PMECR_WKEVT_ENERGY (0x1 << 2)
241 #define PMECR_WKEVT_LINK (0x2 << 2)
242 #define PMECR_WKEVT_MAGICPKT (0x4 << 2)
243 #define PMECR_WKEVT_FRAME (0x8 << 2)
244 #define PMECR_PM_MASK (0x3 << 0)
245 #define PMECR_PM_SHIFT (0)
246 #define PMECR_PM_NORMAL (0x0 << 0)
247 #define PMECR_PM_ENERGY (0x1 << 0)
248 #define PMECR_PM_SOFTDOWN (0x2 << 0)
249 #define PMECR_PM_POWERSAVE (0x3 << 0)
251 /* Standard MII PHY data */
252 #define KS_P1MBCR 0xE4
253 #define KS_P1MBSR 0xE6
254 #define KS_PHY1ILR 0xE8
255 #define KS_PHY1IHR 0xEA
256 #define KS_P1ANAR 0xEC
257 #define KS_P1ANLPR 0xEE
259 #define KS_P1SCLMD 0xF4
260 #define P1SCLMD_LEDOFF (1 << 15)
261 #define P1SCLMD_TXIDS (1 << 14)
262 #define P1SCLMD_RESTARTAN (1 << 13)
263 #define P1SCLMD_DISAUTOMDIX (1 << 10)
264 #define P1SCLMD_FORCEMDIX (1 << 9)
265 #define P1SCLMD_AUTONEGEN (1 << 7)
266 #define P1SCLMD_FORCE100 (1 << 6)
267 #define P1SCLMD_FORCEFDX (1 << 5)
268 #define P1SCLMD_ADV_FLOW (1 << 4)
269 #define P1SCLMD_ADV_100BT_FDX (1 << 3)
270 #define P1SCLMD_ADV_100BT_HDX (1 << 2)
271 #define P1SCLMD_ADV_10BT_FDX (1 << 1)
272 #define P1SCLMD_ADV_10BT_HDX (1 << 0)
274 #define KS_P1CR 0xF6
275 #define P1CR_HP_MDIX (1 << 15)
276 #define P1CR_REV_POL (1 << 13)
277 #define P1CR_OP_100M (1 << 10)
278 #define P1CR_OP_FDX (1 << 9)
279 #define P1CR_OP_MDI (1 << 7)
280 #define P1CR_AN_DONE (1 << 6)
281 #define P1CR_LINK_GOOD (1 << 5)
282 #define P1CR_PNTR_FLOW (1 << 4)
283 #define P1CR_PNTR_100BT_FDX (1 << 3)
284 #define P1CR_PNTR_100BT_HDX (1 << 2)
285 #define P1CR_PNTR_10BT_FDX (1 << 1)
286 #define P1CR_PNTR_10BT_HDX (1 << 0)
288 /* TX Frame control */
290 #define TXFR_TXIC (1 << 15)
291 #define TXFR_TXFID_MASK (0x3f << 0)
292 #define TXFR_TXFID_SHIFT (0)
294 /* SPI frame opcodes */
295 #define KS_SPIOP_RD (0x00)
296 #define KS_SPIOP_WR (0x40)
297 #define KS_SPIOP_RXFIFO (0x80)
298 #define KS_SPIOP_TXFIFO (0xC0)