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powerpc/eeh: Fix PE#0 check in eeh_add_to_parent_pe()
[linux/fpc-iii.git] / drivers / net / wireless / mwifiex / sdio.h
blob957cca24661828c4574f66bee9ac0ecd0126e5b8
1 /*
2 * Marvell Wireless LAN device driver: SDIO specific definitions
3 *
4 * Copyright (C) 2011-2014, Marvell International Ltd.
5 *
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13 *
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
18 */
19
20 #ifndef _MWIFIEX_SDIO_H
21 #define _MWIFIEX_SDIO_H
22
23
24 #include <linux/mmc/sdio.h>
25 #include <linux/mmc/sdio_ids.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/mmc/host.h>
29
30 #include "main.h"
31
32 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
33 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
34 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
35 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
36 #define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
37 #define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin"
38
39 #define BLOCK_MODE 1
40 #define BYTE_MODE 0
41
42 #define REG_PORT 0
43
44 #define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
45
46 #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
47
48 #define MWIFIEX_MAX_FUNC2_REG_NUM 13
49 #define MWIFIEX_SDIO_SCRATCH_SIZE 10
50
51 #define SDIO_MPA_ADDR_BASE 0x1000
52 #define CTRL_PORT 0
53 #define CTRL_PORT_MASK 0x0001
54
55 #define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
56 #define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
57 #define HOST_TERM_CMD53 (0x1U << 2)
58 #define REG_PORT 0
59 #define MEM_PORT 0x10000
60
61 #define CMD53_NEW_MODE (0x1U << 0)
62 #define CMD_PORT_RD_LEN_EN (0x1U << 2)
63 #define CMD_PORT_AUTO_EN (0x1U << 0)
64 #define CMD_PORT_SLCT 0x8000
65 #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
66 #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
67
68 #define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384)
69 #define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768)
70
71 /* Misc. Config Register : Auto Re-enable interrupts */
72 #define AUTO_RE_ENABLE_INT BIT(4)
73
74 /* Host Control Registers : Configuration */
75 #define CONFIGURATION_REG 0x00
76 /* Host Control Registers : Host power up */
77 #define HOST_POWER_UP (0x1U << 1)
78
79 /* Host Control Registers : Upload host interrupt mask */
80 #define UP_LD_HOST_INT_MASK (0x1U)
81 /* Host Control Registers : Download host interrupt mask */
82 #define DN_LD_HOST_INT_MASK (0x2U)
83
84 /* Host Control Registers : Upload host interrupt status */
85 #define UP_LD_HOST_INT_STATUS (0x1U)
86 /* Host Control Registers : Download host interrupt status */
87 #define DN_LD_HOST_INT_STATUS (0x2U)
88
89 /* Host Control Registers : Host interrupt status */
90 #define CARD_INT_STATUS_REG 0x28
91
92 /* Card Control Registers : Card I/O ready */
93 #define CARD_IO_READY (0x1U << 3)
94 /* Card Control Registers : Download card ready */
95 #define DN_LD_CARD_RDY (0x1U << 0)
96
97 /* Max retry number of CMD53 write */
98 #define MAX_WRITE_IOMEM_RETRY 2
99
100 /* SDIO Tx aggregation in progress ? */
101 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
102
103 /* SDIO Tx aggregation buffer room for next packet ? */
104 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
105 <= a->mpa_tx.buf_size)
106
107 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
108 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
109 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
110 payload, pkt_len); \
111 a->mpa_tx.buf_len += pkt_len; \
112 if (!a->mpa_tx.pkt_cnt) \
113 a->mpa_tx.start_port = port; \
114 if (a->mpa_tx.start_port <= port) \
115 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
116 else \
117 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \
118 (a->max_ports - \
119 a->mp_end_port))); \
120 a->mpa_tx.pkt_cnt++; \
121 } while (0)
122
123 /* SDIO Tx aggregation limit ? */
124 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
125 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
126
127 /* Reset SDIO Tx aggregation buffer parameters */
128 #define MP_TX_AGGR_BUF_RESET(a) do { \
129 a->mpa_tx.pkt_cnt = 0; \
130 a->mpa_tx.buf_len = 0; \
131 a->mpa_tx.ports = 0; \
132 a->mpa_tx.start_port = 0; \
133 } while (0)
134
135 /* SDIO Rx aggregation limit ? */
136 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
137 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
138
139 /* SDIO Rx aggregation in progress ? */
140 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
141
142 /* SDIO Rx aggregation buffer room for next packet ? */
143 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
144 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
145
146 /* Reset SDIO Rx aggregation buffer parameters */
147 #define MP_RX_AGGR_BUF_RESET(a) do { \
148 a->mpa_rx.pkt_cnt = 0; \
149 a->mpa_rx.buf_len = 0; \
150 a->mpa_rx.ports = 0; \
151 a->mpa_rx.start_port = 0; \
152 } while (0)
153
154 /* data structure for SDIO MPA TX */
155 struct mwifiex_sdio_mpa_tx {
156 /* multiport tx aggregation buffer pointer */
157 u8 *buf;
158 u32 buf_len;
159 u32 pkt_cnt;
160 u32 ports;
161 u16 start_port;
162 u8 enabled;
163 u32 buf_size;
164 u32 pkt_aggr_limit;
165 };
166
167 struct mwifiex_sdio_mpa_rx {
168 u8 *buf;
169 u32 buf_len;
170 u32 pkt_cnt;
171 u32 ports;
172 u16 start_port;
173
174 struct sk_buff **skb_arr;
175 u32 *len_arr;
176
177 u8 enabled;
178 u32 buf_size;
179 u32 pkt_aggr_limit;
180 };
181
182 int mwifiex_bus_register(void);
183 void mwifiex_bus_unregister(void);
184
185 struct mwifiex_sdio_card_reg {
186 u8 start_rd_port;
187 u8 start_wr_port;
188 u8 base_0_reg;
189 u8 base_1_reg;
190 u8 poll_reg;
191 u8 host_int_enable;
192 u8 host_int_rsr_reg;
193 u8 host_int_status_reg;
194 u8 host_int_mask_reg;
195 u8 status_reg_0;
196 u8 status_reg_1;
197 u8 sdio_int_mask;
198 u32 data_port_mask;
199 u8 io_port_0_reg;
200 u8 io_port_1_reg;
201 u8 io_port_2_reg;
202 u8 max_mp_regs;
203 u8 rd_bitmap_l;
204 u8 rd_bitmap_u;
205 u8 rd_bitmap_1l;
206 u8 rd_bitmap_1u;
207 u8 wr_bitmap_l;
208 u8 wr_bitmap_u;
209 u8 wr_bitmap_1l;
210 u8 wr_bitmap_1u;
211 u8 rd_len_p0_l;
212 u8 rd_len_p0_u;
213 u8 card_misc_cfg_reg;
214 u8 card_cfg_2_1_reg;
215 u8 cmd_rd_len_0;
216 u8 cmd_rd_len_1;
217 u8 cmd_rd_len_2;
218 u8 cmd_rd_len_3;
219 u8 cmd_cfg_0;
220 u8 cmd_cfg_1;
221 u8 cmd_cfg_2;
222 u8 cmd_cfg_3;
223 u8 fw_dump_ctrl;
224 u8 fw_dump_start;
225 u8 fw_dump_end;
226 u8 func1_dump_reg_start;
227 u8 func1_dump_reg_end;
228 u8 func1_scratch_reg;
229 u8 func1_spec_reg_num;
230 u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM];
231 };
232
233 struct sdio_mmc_card {
234 struct sdio_func *func;
235 struct mwifiex_adapter *adapter;
236
237 const char *firmware;
238 const struct mwifiex_sdio_card_reg *reg;
239 u8 max_ports;
240 u8 mp_agg_pkt_limit;
241 bool supports_sdio_new_mode;
242 bool has_control_mask;
243 bool supports_fw_dump;
244 u16 tx_buf_size;
245 u32 mp_tx_agg_buf_size;
246 u32 mp_rx_agg_buf_size;
247
248 u32 mp_rd_bitmap;
249 u32 mp_wr_bitmap;
250
251 u16 mp_end_port;
252 u32 mp_data_port_mask;
253
254 u8 curr_rd_port;
255 u8 curr_wr_port;
256
257 u8 *mp_regs;
258 u8 auto_tdls;
259 bool can_ext_scan;
260
261 struct mwifiex_sdio_mpa_tx mpa_tx;
262 struct mwifiex_sdio_mpa_rx mpa_rx;
263 };
264
265 struct mwifiex_sdio_device {
266 const char *firmware;
267 const struct mwifiex_sdio_card_reg *reg;
268 u8 max_ports;
269 u8 mp_agg_pkt_limit;
270 bool supports_sdio_new_mode;
271 bool has_control_mask;
272 bool supports_fw_dump;
273 u16 tx_buf_size;
274 u32 mp_tx_agg_buf_size;
275 u32 mp_rx_agg_buf_size;
276 u8 auto_tdls;
277 bool can_ext_scan;
278 };
279
280 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
281 .start_rd_port = 1,
282 .start_wr_port = 1,
283 .base_0_reg = 0x0040,
284 .base_1_reg = 0x0041,
285 .poll_reg = 0x30,
286 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
287 .host_int_rsr_reg = 0x1,
288 .host_int_mask_reg = 0x02,
289 .host_int_status_reg = 0x03,
290 .status_reg_0 = 0x60,
291 .status_reg_1 = 0x61,
292 .sdio_int_mask = 0x3f,
293 .data_port_mask = 0x0000fffe,
294 .io_port_0_reg = 0x78,
295 .io_port_1_reg = 0x79,
296 .io_port_2_reg = 0x7A,
297 .max_mp_regs = 64,
298 .rd_bitmap_l = 0x04,
299 .rd_bitmap_u = 0x05,
300 .wr_bitmap_l = 0x06,
301 .wr_bitmap_u = 0x07,
302 .rd_len_p0_l = 0x08,
303 .rd_len_p0_u = 0x09,
304 .card_misc_cfg_reg = 0x6c,
305 .func1_dump_reg_start = 0x0,
306 .func1_dump_reg_end = 0x9,
307 .func1_scratch_reg = 0x60,
308 .func1_spec_reg_num = 5,
309 .func1_spec_reg_table = {0x28, 0x30, 0x34, 0x38, 0x3c},
310 };
311
312 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
313 .start_rd_port = 0,
314 .start_wr_port = 0,
315 .base_0_reg = 0x60,
316 .base_1_reg = 0x61,
317 .poll_reg = 0x50,
318 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
319 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
320 .host_int_rsr_reg = 0x1,
321 .host_int_status_reg = 0x03,
322 .host_int_mask_reg = 0x02,
323 .status_reg_0 = 0xc0,
324 .status_reg_1 = 0xc1,
325 .sdio_int_mask = 0xff,
326 .data_port_mask = 0xffffffff,
327 .io_port_0_reg = 0xD8,
328 .io_port_1_reg = 0xD9,
329 .io_port_2_reg = 0xDA,
330 .max_mp_regs = 184,
331 .rd_bitmap_l = 0x04,
332 .rd_bitmap_u = 0x05,
333 .rd_bitmap_1l = 0x06,
334 .rd_bitmap_1u = 0x07,
335 .wr_bitmap_l = 0x08,
336 .wr_bitmap_u = 0x09,
337 .wr_bitmap_1l = 0x0a,
338 .wr_bitmap_1u = 0x0b,
339 .rd_len_p0_l = 0x0c,
340 .rd_len_p0_u = 0x0d,
341 .card_misc_cfg_reg = 0xcc,
342 .card_cfg_2_1_reg = 0xcd,
343 .cmd_rd_len_0 = 0xb4,
344 .cmd_rd_len_1 = 0xb5,
345 .cmd_rd_len_2 = 0xb6,
346 .cmd_rd_len_3 = 0xb7,
347 .cmd_cfg_0 = 0xb8,
348 .cmd_cfg_1 = 0xb9,
349 .cmd_cfg_2 = 0xba,
350 .cmd_cfg_3 = 0xbb,
351 .fw_dump_ctrl = 0xe2,
352 .fw_dump_start = 0xe3,
353 .fw_dump_end = 0xea,
354 .func1_dump_reg_start = 0x0,
355 .func1_dump_reg_end = 0xb,
356 .func1_scratch_reg = 0xc0,
357 .func1_spec_reg_num = 8,
358 .func1_spec_reg_table = {0x4C, 0x50, 0x54, 0x55, 0x58,
359 0x59, 0x5c, 0x5d},
360 };
361
362 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = {
363 .start_rd_port = 0,
364 .start_wr_port = 0,
365 .base_0_reg = 0x6C,
366 .base_1_reg = 0x6D,
367 .poll_reg = 0x5C,
368 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
369 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
370 .host_int_rsr_reg = 0x4,
371 .host_int_status_reg = 0x0C,
372 .host_int_mask_reg = 0x08,
373 .status_reg_0 = 0x90,
374 .status_reg_1 = 0x91,
375 .sdio_int_mask = 0xff,
376 .data_port_mask = 0xffffffff,
377 .io_port_0_reg = 0xE4,
378 .io_port_1_reg = 0xE5,
379 .io_port_2_reg = 0xE6,
380 .max_mp_regs = 196,
381 .rd_bitmap_l = 0x10,
382 .rd_bitmap_u = 0x11,
383 .rd_bitmap_1l = 0x12,
384 .rd_bitmap_1u = 0x13,
385 .wr_bitmap_l = 0x14,
386 .wr_bitmap_u = 0x15,
387 .wr_bitmap_1l = 0x16,
388 .wr_bitmap_1u = 0x17,
389 .rd_len_p0_l = 0x18,
390 .rd_len_p0_u = 0x19,
391 .card_misc_cfg_reg = 0xd8,
392 .card_cfg_2_1_reg = 0xd9,
393 .cmd_rd_len_0 = 0xc0,
394 .cmd_rd_len_1 = 0xc1,
395 .cmd_rd_len_2 = 0xc2,
396 .cmd_rd_len_3 = 0xc3,
397 .cmd_cfg_0 = 0xc4,
398 .cmd_cfg_1 = 0xc5,
399 .cmd_cfg_2 = 0xc6,
400 .cmd_cfg_3 = 0xc7,
401 .func1_dump_reg_start = 0x10,
402 .func1_dump_reg_end = 0x17,
403 .func1_scratch_reg = 0x90,
404 .func1_spec_reg_num = 13,
405 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60,
406 0x61, 0x62, 0x64, 0x65, 0x66,
407 0x68, 0x69, 0x6a},
408 };
409
410 static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
411 .firmware = SD8786_DEFAULT_FW_NAME,
412 .reg = &mwifiex_reg_sd87xx,
413 .max_ports = 16,
414 .mp_agg_pkt_limit = 8,
415 .supports_sdio_new_mode = false,
416 .has_control_mask = true,
417 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
418 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
419 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
420 .supports_fw_dump = false,
421 .auto_tdls = false,
422 .can_ext_scan = false,
423 };
424
425 static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
426 .firmware = SD8787_DEFAULT_FW_NAME,
427 .reg = &mwifiex_reg_sd87xx,
428 .max_ports = 16,
429 .mp_agg_pkt_limit = 8,
430 .supports_sdio_new_mode = false,
431 .has_control_mask = true,
432 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
433 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
434 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
435 .supports_fw_dump = false,
436 .auto_tdls = false,
437 .can_ext_scan = true,
438 };
439
440 static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
441 .firmware = SD8797_DEFAULT_FW_NAME,
442 .reg = &mwifiex_reg_sd87xx,
443 .max_ports = 16,
444 .mp_agg_pkt_limit = 8,
445 .supports_sdio_new_mode = false,
446 .has_control_mask = true,
447 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
448 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
449 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
450 .supports_fw_dump = false,
451 .auto_tdls = false,
452 .can_ext_scan = true,
453 };
454
455 static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
456 .firmware = SD8897_DEFAULT_FW_NAME,
457 .reg = &mwifiex_reg_sd8897,
458 .max_ports = 32,
459 .mp_agg_pkt_limit = 16,
460 .supports_sdio_new_mode = true,
461 .has_control_mask = false,
462 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
463 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
464 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
465 .supports_fw_dump = true,
466 .auto_tdls = false,
467 .can_ext_scan = true,
468 };
469
470 static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = {
471 .firmware = SD8887_DEFAULT_FW_NAME,
472 .reg = &mwifiex_reg_sd8887,
473 .max_ports = 32,
474 .mp_agg_pkt_limit = 16,
475 .supports_sdio_new_mode = true,
476 .has_control_mask = false,
477 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
478 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
479 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
480 .supports_fw_dump = false,
481 .auto_tdls = true,
482 .can_ext_scan = true,
483 };
484
485 static const struct mwifiex_sdio_device mwifiex_sdio_sd8801 = {
486 .firmware = SD8801_DEFAULT_FW_NAME,
487 .reg = &mwifiex_reg_sd87xx,
488 .max_ports = 16,
489 .mp_agg_pkt_limit = 8,
490 .supports_sdio_new_mode = false,
491 .has_control_mask = true,
492 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
493 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
494 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
495 .supports_fw_dump = false,
496 .auto_tdls = false,
497 .can_ext_scan = true,
498 };
499
500 /*
501 * .cmdrsp_complete handler
502 */
503 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
504 struct sk_buff *skb)
505 {
506 dev_kfree_skb_any(skb);
507 return 0;
508 }
509
510 /*
511 * .event_complete handler
512 */
513 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
514 struct sk_buff *skb)
515 {
516 dev_kfree_skb_any(skb);
517 return 0;
518 }
519
520 static inline bool
521 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
522 {
523 u8 tmp;
524
525 if (card->curr_rd_port < card->mpa_rx.start_port) {
526 if (card->supports_sdio_new_mode)
527 tmp = card->mp_end_port >> 1;
528 else
529 tmp = card->mp_agg_pkt_limit;
530
531 if (((card->max_ports - card->mpa_rx.start_port) +
532 card->curr_rd_port) >= tmp)
533 return true;
534 }
535
536 if (!card->supports_sdio_new_mode)
537 return false;
538
539 if ((card->curr_rd_port - card->mpa_rx.start_port) >=
540 (card->mp_end_port >> 1))
541 return true;
542
543 return false;
544 }
545
546 static inline bool
547 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
548 {
549 u16 tmp;
550
551 if (card->curr_wr_port < card->mpa_tx.start_port) {
552 if (card->supports_sdio_new_mode)
553 tmp = card->mp_end_port >> 1;
554 else
555 tmp = card->mp_agg_pkt_limit;
556
557 if (((card->max_ports - card->mpa_tx.start_port) +
558 card->curr_wr_port) >= tmp)
559 return true;
560 }
561
562 if (!card->supports_sdio_new_mode)
563 return false;
564
565 if ((card->curr_wr_port - card->mpa_tx.start_port) >=
566 (card->mp_end_port >> 1))
567 return true;
568
569 return false;
570 }
571
572 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
573 static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
574 struct sk_buff *skb, u8 port)
575 {
576 card->mpa_rx.buf_len += skb->len;
577
578 if (!card->mpa_rx.pkt_cnt)
579 card->mpa_rx.start_port = port;
580
581 if (card->supports_sdio_new_mode) {
582 card->mpa_rx.ports |= (1 << port);
583 } else {
584 if (card->mpa_rx.start_port <= port)
585 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
586 else
587 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
588 }
589 card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = skb;
590 card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = skb->len;
591 card->mpa_rx.pkt_cnt++;
592 }
593 #endif /* _MWIFIEX_SDIO_H */
Linux with added FPC-III support