1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *****************************************************************************/
25 #ifndef __RTL_DEBUG_H__
26 #define __RTL_DEBUG_H__
28 /*--------------------------------------------------------------
30 --------------------------------------------------------------*/
33 *For example, Tx/Rx/IO locked up,
34 *memory access violation,
35 *resource allocation failed,
36 *unexpected HW behavior, HW BUG
42 *Abnormal, rare, or unexpeted cases.
43 *For example, Packet/IO Ctl canceled,
44 *device suprisely unremoved and so on.
49 *Normal case driver developer should
50 *open, we can see link status like
51 *assoc/AddBA/DHCP/adapter start and
52 *so on basic and useful infromations.
57 *Normal case with useful information
58 *about current SW or HW state.
59 *For example, Tx/Rx descriptor to fill,
60 *Tx/Rx descriptor completed status,
61 *SW protocol state change, dynamic
62 *mechanism state change and so on.
67 *Normal case with detail execution
72 /*--------------------------------------------------------------
73 Define the rt_trace components
74 --------------------------------------------------------------*/
75 #define COMP_ERR BIT(0)
76 #define COMP_FW BIT(1)
77 #define COMP_INIT BIT(2) /*For init/deinit */
78 #define COMP_RECV BIT(3) /*For Rx. */
79 #define COMP_SEND BIT(4) /*For Tx. */
80 #define COMP_MLME BIT(5) /*For MLME. */
81 #define COMP_SCAN BIT(6) /*For Scan. */
82 #define COMP_INTR BIT(7) /*For interrupt Related. */
83 #define COMP_LED BIT(8) /*For LED. */
84 #define COMP_SEC BIT(9) /*For sec. */
85 #define COMP_BEACON BIT(10) /*For beacon. */
86 #define COMP_RATE BIT(11) /*For rate. */
87 #define COMP_RXDESC BIT(12) /*For rx desc. */
88 #define COMP_DIG BIT(13) /*For DIG */
89 #define COMP_TXAGC BIT(14) /*For Tx power */
90 #define COMP_HIPWR BIT(15) /*For High Power Mechanism */
91 #define COMP_POWER BIT(16) /*For lps/ips/aspm. */
92 #define COMP_POWER_TRACKING BIT(17) /*For TX POWER TRACKING */
93 #define COMP_BB_POWERSAVING BIT(18)
94 #define COMP_SWAS BIT(19) /*For SW Antenna Switch */
95 #define COMP_RF BIT(20) /*For RF. */
96 #define COMP_TURBO BIT(21) /*For EDCA TURBO. */
97 #define COMP_RATR BIT(22)
98 #define COMP_CMD BIT(23)
99 #define COMP_EFUSE BIT(24)
100 #define COMP_QOS BIT(25)
101 #define COMP_MAC80211 BIT(26)
102 #define COMP_REGD BIT(27)
103 #define COMP_CHAN BIT(28)
104 #define COMP_USB BIT(29)
105 #define COMP_EASY_CONCURRENT COMP_USB /* reuse of this bit is OK */
106 #define COMP_BT_COEXIST BIT(30)
107 #define COMP_IQK BIT(31)
109 /*--------------------------------------------------------------
110 Define the rt_print components
111 --------------------------------------------------------------*/
112 /* Define EEPROM and EFUSE check module bit*/
113 #define EEPROM_W BIT(0)
114 #define EFUSE_PG BIT(1)
115 #define EFUSE_READ_ALL BIT(2)
117 /* Define init check for module bit*/
118 #define INIT_EEPROM BIT(0)
119 #define INIT_TXPOWER BIT(1)
120 #define INIT_IQK BIT(2)
121 #define INIT_RF BIT(3)
123 /* Define PHY-BB/RF/MAC check module bit */
124 #define PHY_BBR BIT(0)
125 #define PHY_BBW BIT(1)
126 #define PHY_RFR BIT(2)
127 #define PHY_RFW BIT(3)
128 #define PHY_MACR BIT(4)
129 #define PHY_MACW BIT(5)
130 #define PHY_ALLR BIT(6)
131 #define PHY_ALLW BIT(7)
132 #define PHY_TXPWR BIT(8)
133 #define PHY_PWRDIFF BIT(9)
135 /* Define Dynamic Mechanism check module bit --> FDM */
136 #define WA_IOT BIT(0)
137 #define DM_PWDB BIT(1)
138 #define DM_MONITOR BIT(2)
139 #define DM_DIG BIT(3)
140 #define DM_EDCA_TURBO BIT(4)
142 #define DM_PWDB BIT(1)
167 #ifdef CONFIG_RTLWIFI_DEBUG
169 #define RT_ASSERT(_exp, fmt, ...) \
172 printk(KERN_DEBUG KBUILD_MODNAME ":%s(): " fmt, \
173 __func__, ##__VA_ARGS__); \
177 #define RT_TRACE(rtlpriv, comp, level, fmt, ...) \
179 if (unlikely(((comp) & rtlpriv->dbg.global_debugcomponents) && \
180 ((level) <= rtlpriv->dbg.global_debuglevel))) { \
181 printk(KERN_DEBUG KBUILD_MODNAME ":%s():<%lx-%x> " fmt, \
182 __func__, in_interrupt(), in_atomic(), \
187 #define RTPRINT(rtlpriv, dbgtype, dbgflag, fmt, ...) \
189 if (unlikely(rtlpriv->dbg.dbgp_type[dbgtype] & dbgflag)) { \
190 printk(KERN_DEBUG KBUILD_MODNAME ": " fmt, \
195 #define RT_PRINT_DATA(rtlpriv, _comp, _level, _titlestring, _hexdata, \
198 if (unlikely(((_comp) & rtlpriv->dbg.global_debugcomponents) && \
199 (_level <= rtlpriv->dbg.global_debuglevel))) { \
200 printk(KERN_DEBUG "%s: In process \"%s\" (pid %i): %s\n", \
201 KBUILD_MODNAME, current->comm, current->pid, \
203 print_hex_dump_bytes("", DUMP_PREFIX_NONE, \
204 _hexdata, _hexdatalen); \
213 static inline void RT_ASSERT(int exp
, const char *fmt
, ...)
218 static inline void RT_TRACE(struct rtl_priv
*rtlpriv
,
220 const char *fmt
, ...)
225 static inline void RTPRINT(struct rtl_priv
*rtlpriv
,
226 int dbgtype
, int dbgflag
,
227 const char *fmt
, ...)
231 static inline void RT_PRINT_DATA(struct rtl_priv
*rtlpriv
,
233 const char *titlestring
,
234 const void *hexdata
, size_t hexdatalen
)
240 void rtl_dbgp_flag_init(struct ieee80211_hw
*hw
);