1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
40 #include "../rtl8192c/dm_common.h"
41 #include "../rtl8192c/fw_common.h"
42 #include "../rtl8192c/phy_common.h"
49 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw
*hw
,
50 u8 set_bits
, u8 clear_bits
)
52 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
53 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
55 rtlpci
->reg_bcn_ctrl_val
|= set_bits
;
56 rtlpci
->reg_bcn_ctrl_val
&= ~clear_bits
;
58 rtl_write_byte(rtlpriv
, REG_BCN_CTRL
, (u8
)rtlpci
->reg_bcn_ctrl_val
);
61 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw
*hw
)
63 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
66 tmp1byte
= rtl_read_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2);
67 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2, tmp1byte
& (~BIT(6)));
68 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0x64);
69 tmp1byte
= rtl_read_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2);
70 tmp1byte
&= ~(BIT(0));
71 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2, tmp1byte
);
74 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw
*hw
)
76 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
79 tmp1byte
= rtl_read_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2);
80 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2, tmp1byte
| BIT(6));
81 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0xff);
82 tmp1byte
= rtl_read_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2);
84 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2, tmp1byte
);
87 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw
*hw
)
89 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(1));
92 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw
*hw
)
94 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(1), 0);
97 void rtl92ce_get_hw_reg(struct ieee80211_hw
*hw
, u8 variable
, u8
*val
)
99 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
100 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
101 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
105 *((u32
*) (val
)) = rtlpci
->receive_config
;
107 case HW_VAR_RF_STATE
:
108 *((enum rf_pwrstate
*)(val
)) = ppsc
->rfpwr_state
;
110 case HW_VAR_FWLPS_RF_ON
:{
111 enum rf_pwrstate rfState
;
114 rtlpriv
->cfg
->ops
->get_hw_reg(hw
,
117 if (rfState
== ERFOFF
) {
118 *((bool *) (val
)) = true;
120 val_rcr
= rtl_read_dword(rtlpriv
, REG_RCR
);
121 val_rcr
&= 0x00070000;
123 *((bool *) (val
)) = false;
125 *((bool *) (val
)) = true;
129 case HW_VAR_FW_PSMODE_STATUS
:
130 *((bool *) (val
)) = ppsc
->fw_current_inpsmode
;
132 case HW_VAR_CORRECT_TSF
:{
134 u32
*ptsf_low
= (u32
*)&tsf
;
135 u32
*ptsf_high
= ((u32
*)&tsf
) + 1;
137 *ptsf_high
= rtl_read_dword(rtlpriv
, (REG_TSFTR
+ 4));
138 *ptsf_low
= rtl_read_dword(rtlpriv
, REG_TSFTR
);
140 *((u64
*) (val
)) = tsf
;
145 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
146 "switch case not processed\n");
151 void rtl92ce_set_hw_reg(struct ieee80211_hw
*hw
, u8 variable
, u8
*val
)
153 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
154 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
155 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
156 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
157 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
158 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
159 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
163 case HW_VAR_ETHER_ADDR
:{
164 for (idx
= 0; idx
< ETH_ALEN
; idx
++) {
165 rtl_write_byte(rtlpriv
, (REG_MACID
+ idx
),
170 case HW_VAR_BASIC_RATE
:{
171 u16 rate_cfg
= ((u16
*) val
)[0];
175 rtl_write_byte(rtlpriv
, REG_RRSR
, rate_cfg
& 0xff);
176 rtl_write_byte(rtlpriv
, REG_RRSR
+ 1,
177 (rate_cfg
>> 8) & 0xff);
178 while (rate_cfg
> 0x1) {
179 rate_cfg
= (rate_cfg
>> 1);
182 rtl_write_byte(rtlpriv
, REG_INIRTS_RATE_SEL
,
187 for (idx
= 0; idx
< ETH_ALEN
; idx
++) {
188 rtl_write_byte(rtlpriv
, (REG_BSSID
+ idx
),
194 rtl_write_byte(rtlpriv
, REG_SIFS_CTX
+ 1, val
[0]);
195 rtl_write_byte(rtlpriv
, REG_SIFS_TRX
+ 1, val
[1]);
197 rtl_write_byte(rtlpriv
, REG_SPEC_SIFS
+ 1, val
[0]);
198 rtl_write_byte(rtlpriv
, REG_MAC_SPEC_SIFS
+ 1, val
[0]);
201 rtl_write_word(rtlpriv
, REG_RESP_SIFS_OFDM
,
204 rtl_write_word(rtlpriv
, REG_RESP_SIFS_OFDM
,
208 case HW_VAR_SLOT_TIME
:{
211 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
212 "HW_VAR_SLOT_TIME %x\n", val
[0]);
214 rtl_write_byte(rtlpriv
, REG_SLOT
, val
[0]);
216 for (e_aci
= 0; e_aci
< AC_MAX
; e_aci
++) {
217 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
223 case HW_VAR_ACK_PREAMBLE
:{
225 u8 short_preamble
= (bool)*val
;
226 reg_tmp
= (mac
->cur_40_prime_sc
) << 5;
230 rtl_write_byte(rtlpriv
, REG_RRSR
+ 2, reg_tmp
);
233 case HW_VAR_AMPDU_MIN_SPACE
:{
234 u8 min_spacing_to_set
;
237 min_spacing_to_set
= *val
;
238 if (min_spacing_to_set
<= 7) {
241 if (min_spacing_to_set
< sec_min_space
)
242 min_spacing_to_set
= sec_min_space
;
244 mac
->min_space_cfg
= ((mac
->min_space_cfg
&
248 *val
= min_spacing_to_set
;
250 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
251 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
254 rtl_write_byte(rtlpriv
, REG_AMPDU_MIN_SPACE
,
259 case HW_VAR_SHORTGI_DENSITY
:{
262 density_to_set
= *val
;
263 mac
->min_space_cfg
|= (density_to_set
<< 3);
265 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
266 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
269 rtl_write_byte(rtlpriv
, REG_AMPDU_MIN_SPACE
,
274 case HW_VAR_AMPDU_FACTOR
:{
275 u8 regtoset_normal
[4] = {0x41, 0xa8, 0x72, 0xb9};
276 u8 regtoset_bt
[4] = {0x31, 0x74, 0x42, 0x97};
279 u8
*p_regtoset
= NULL
;
282 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
283 (rtlpcipriv
->bt_coexist
.bt_coexist_type
==
285 p_regtoset
= regtoset_bt
;
287 p_regtoset
= regtoset_normal
;
289 factor_toset
= *(val
);
290 if (factor_toset
<= 3) {
291 factor_toset
= (1 << (factor_toset
+ 2));
292 if (factor_toset
> 0xf)
295 for (index
= 0; index
< 4; index
++) {
296 if ((p_regtoset
[index
] & 0xf0) >
299 (p_regtoset
[index
] & 0x0f) |
302 if ((p_regtoset
[index
] & 0x0f) >
305 (p_regtoset
[index
] & 0xf0) |
308 rtl_write_byte(rtlpriv
,
309 (REG_AGGLEN_LMT
+ index
),
314 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
315 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
320 case HW_VAR_AC_PARAM
:{
322 rtl92c_dm_init_edca_turbo(hw
);
324 if (rtlpci
->acm_method
!= EACMWAY2_SW
)
325 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
330 case HW_VAR_ACM_CTRL
:{
332 union aci_aifsn
*p_aci_aifsn
=
333 (union aci_aifsn
*)(&(mac
->ac
[0].aifs
));
334 u8 acm
= p_aci_aifsn
->f
.acm
;
335 u8 acm_ctrl
= rtl_read_byte(rtlpriv
, REG_ACMHWCTRL
);
338 acm_ctrl
| ((rtlpci
->acm_method
== 2) ? 0x0 : 0x1);
343 acm_ctrl
|= AcmHw_BeqEn
;
346 acm_ctrl
|= AcmHw_ViqEn
;
349 acm_ctrl
|= AcmHw_VoqEn
;
352 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
353 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
360 acm_ctrl
&= (~AcmHw_BeqEn
);
363 acm_ctrl
&= (~AcmHw_ViqEn
);
366 acm_ctrl
&= (~AcmHw_BeqEn
);
369 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
370 "switch case not processed\n");
375 RT_TRACE(rtlpriv
, COMP_QOS
, DBG_TRACE
,
376 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
378 rtl_write_byte(rtlpriv
, REG_ACMHWCTRL
, acm_ctrl
);
382 rtl_write_dword(rtlpriv
, REG_RCR
, ((u32
*) (val
))[0]);
383 rtlpci
->receive_config
= ((u32
*) (val
))[0];
386 case HW_VAR_RETRY_LIMIT
:{
387 u8 retry_limit
= val
[0];
389 rtl_write_word(rtlpriv
, REG_RL
,
390 retry_limit
<< RETRY_LIMIT_SHORT_SHIFT
|
391 retry_limit
<< RETRY_LIMIT_LONG_SHIFT
);
394 case HW_VAR_DUAL_TSF_RST
:
395 rtl_write_byte(rtlpriv
, REG_DUAL_TSF_RST
, (BIT(0) | BIT(1)));
397 case HW_VAR_EFUSE_BYTES
:
398 rtlefuse
->efuse_usedbytes
= *((u16
*) val
);
400 case HW_VAR_EFUSE_USAGE
:
401 rtlefuse
->efuse_usedpercentage
= *val
;
404 rtl92c_phy_set_io_cmd(hw
, (*(enum io_type
*)val
));
406 case HW_VAR_WPA_CONFIG
:
407 rtl_write_byte(rtlpriv
, REG_SECCFG
, *val
);
409 case HW_VAR_SET_RPWM
:{
412 rpwm_val
= rtl_read_byte(rtlpriv
, REG_PCIE_HRPWM
);
415 if (rpwm_val
& BIT(7)) {
416 rtl_write_byte(rtlpriv
, REG_PCIE_HRPWM
, *val
);
418 rtl_write_byte(rtlpriv
, REG_PCIE_HRPWM
,
424 case HW_VAR_H2C_FW_PWRMODE
:{
427 if ((psmode
!= FW_PS_ACTIVE_MODE
) &&
428 (!IS_92C_SERIAL(rtlhal
->version
))) {
429 rtl92c_dm_rf_saving(hw
, true);
432 rtl92c_set_fw_pwrmode_cmd(hw
, *val
);
435 case HW_VAR_FW_PSMODE_STATUS
:
436 ppsc
->fw_current_inpsmode
= *((bool *) val
);
438 case HW_VAR_H2C_FW_JOINBSSRPT
:{
440 u8 tmp_regcr
, tmp_reg422
;
441 bool recover
= false;
443 if (mstatus
== RT_MEDIA_CONNECT
) {
444 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_AID
,
447 tmp_regcr
= rtl_read_byte(rtlpriv
, REG_CR
+ 1);
448 rtl_write_byte(rtlpriv
, REG_CR
+ 1,
449 (tmp_regcr
| BIT(0)));
451 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(3));
452 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(4), 0);
455 rtl_read_byte(rtlpriv
,
456 REG_FWHW_TXQ_CTRL
+ 2);
457 if (tmp_reg422
& BIT(6))
459 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2,
460 tmp_reg422
& (~BIT(6)));
462 rtl92c_set_fw_rsvdpagepkt(hw
, NULL
);
464 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(3), 0);
465 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(4));
468 rtl_write_byte(rtlpriv
,
469 REG_FWHW_TXQ_CTRL
+ 2,
473 rtl_write_byte(rtlpriv
, REG_CR
+ 1,
474 (tmp_regcr
& ~(BIT(0))));
476 rtl92c_set_fw_joinbss_report_cmd(hw
, *val
);
480 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD
:
481 rtl92c_set_p2p_ps_offload_cmd(hw
, *val
);
485 u2btmp
= rtl_read_word(rtlpriv
, REG_BCN_PSR_RPT
);
487 rtl_write_word(rtlpriv
, REG_BCN_PSR_RPT
, (u2btmp
|
492 case HW_VAR_CORRECT_TSF
:{
493 u8 btype_ibss
= val
[0];
496 _rtl92ce_stop_tx_beacon(hw
);
498 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(3));
500 rtl_write_dword(rtlpriv
, REG_TSFTR
,
501 (u32
) (mac
->tsf
& 0xffffffff));
502 rtl_write_dword(rtlpriv
, REG_TSFTR
+ 4,
503 (u32
) ((mac
->tsf
>> 32) & 0xffffffff));
505 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(3), 0);
508 _rtl92ce_resume_tx_beacon(hw
);
513 case HW_VAR_FW_LPS_ACTION
: {
514 bool enter_fwlps
= *((bool *)val
);
515 u8 rpwm_val
, fw_pwrmode
;
516 bool fw_current_inps
;
519 rpwm_val
= 0x02; /* RF off */
520 fw_current_inps
= true;
521 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
522 HW_VAR_FW_PSMODE_STATUS
,
523 (u8
*)(&fw_current_inps
));
524 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
525 HW_VAR_H2C_FW_PWRMODE
,
526 &ppsc
->fwctrl_psmode
);
528 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
532 rpwm_val
= 0x0C; /* RF on */
533 fw_pwrmode
= FW_PS_ACTIVE_MODE
;
534 fw_current_inps
= false;
535 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
538 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
539 HW_VAR_H2C_FW_PWRMODE
,
542 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
543 HW_VAR_FW_PSMODE_STATUS
,
544 (u8
*)(&fw_current_inps
));
547 case HW_VAR_KEEP_ALIVE
: {
551 array
[1] = *((u8
*)val
);
552 rtl92c_fill_h2c_cmd(hw
, H2C_92C_KEEP_ALIVE_CTRL
, 2, array
);
555 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
556 "switch case %d not processed\n", variable
);
561 static bool _rtl92ce_llt_write(struct ieee80211_hw
*hw
, u32 address
, u32 data
)
563 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
566 u32 value
= _LLT_INIT_ADDR(address
) |
567 _LLT_INIT_DATA(data
) | _LLT_OP(_LLT_WRITE_ACCESS
);
569 rtl_write_dword(rtlpriv
, REG_LLT_INIT
, value
);
572 value
= rtl_read_dword(rtlpriv
, REG_LLT_INIT
);
573 if (_LLT_NO_ACTIVE
== _LLT_OP_VALUE(value
))
576 if (count
> POLLING_LLT_THRESHOLD
) {
577 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
578 "Failed to polling write LLT done at address %d!\n",
588 static bool _rtl92ce_llt_table_init(struct ieee80211_hw
*hw
)
590 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
599 #elif LLT_CONFIG == 2
602 #elif LLT_CONFIG == 3
605 #elif LLT_CONFIG == 4
608 #elif LLT_CONFIG == 5
614 rtl_write_byte(rtlpriv
, REG_RQPN_NPQ
, 0x1c);
615 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x80a71c1c);
616 #elif LLT_CONFIG == 2
617 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x845B1010);
618 #elif LLT_CONFIG == 3
619 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x84838484);
620 #elif LLT_CONFIG == 4
621 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x80bd1c1c);
622 #elif LLT_CONFIG == 5
623 rtl_write_word(rtlpriv
, REG_RQPN_NPQ
, 0x0000);
625 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x80b01c29);
628 rtl_write_dword(rtlpriv
, REG_TRXFF_BNDY
, (0x27FF0000 | txpktbuf_bndy
));
629 rtl_write_byte(rtlpriv
, REG_TDECTRL
+ 1, txpktbuf_bndy
);
631 rtl_write_byte(rtlpriv
, REG_TXPKTBUF_BCNQ_BDNY
, txpktbuf_bndy
);
632 rtl_write_byte(rtlpriv
, REG_TXPKTBUF_MGQ_BDNY
, txpktbuf_bndy
);
634 rtl_write_byte(rtlpriv
, 0x45D, txpktbuf_bndy
);
635 rtl_write_byte(rtlpriv
, REG_PBP
, 0x11);
636 rtl_write_byte(rtlpriv
, REG_RX_DRVINFO_SZ
, 0x4);
638 for (i
= 0; i
< (txpktbuf_bndy
- 1); i
++) {
639 status
= _rtl92ce_llt_write(hw
, i
, i
+ 1);
644 status
= _rtl92ce_llt_write(hw
, (txpktbuf_bndy
- 1), 0xFF);
648 for (i
= txpktbuf_bndy
; i
< maxPage
; i
++) {
649 status
= _rtl92ce_llt_write(hw
, i
, (i
+ 1));
654 status
= _rtl92ce_llt_write(hw
, maxPage
, txpktbuf_bndy
);
661 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw
*hw
)
663 struct rtl_pci_priv
*pcipriv
= rtl_pcipriv(hw
);
664 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
665 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
666 struct rtl_led
*pLed0
= &(pcipriv
->ledctl
.sw_led0
);
668 if (rtlpci
->up_first_time
)
671 if (ppsc
->rfoff_reason
== RF_CHANGE_BY_IPS
)
672 rtl92ce_sw_led_on(hw
, pLed0
);
673 else if (ppsc
->rfoff_reason
== RF_CHANGE_BY_INIT
)
674 rtl92ce_sw_led_on(hw
, pLed0
);
676 rtl92ce_sw_led_off(hw
, pLed0
);
679 static bool _rtl92ce_init_mac(struct ieee80211_hw
*hw
)
681 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
682 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
683 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
684 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
686 unsigned char bytetmp
;
687 unsigned short wordtmp
;
690 rtl_write_byte(rtlpriv
, REG_RSV_CTRL
, 0x00);
691 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
693 value32
= rtl_read_dword(rtlpriv
, REG_APS_FSMCO
);
694 value32
|= (SOP_ABG
| SOP_AMB
| XOP_BTCK
);
695 rtl_write_dword(rtlpriv
, REG_APS_FSMCO
, value32
);
697 rtl_write_byte(rtlpriv
, REG_SPS0_CTRL
, 0x2b);
698 rtl_write_byte(rtlpriv
, REG_AFE_XTAL_CTRL
, 0x0F);
700 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
701 u32 u4b_tmp
= rtl_read_dword(rtlpriv
, REG_AFE_XTAL_CTRL
);
703 u4b_tmp
&= (~0x00024800);
704 rtl_write_dword(rtlpriv
, REG_AFE_XTAL_CTRL
, u4b_tmp
);
707 bytetmp
= rtl_read_byte(rtlpriv
, REG_APS_FSMCO
+ 1) | BIT(0);
710 rtl_write_byte(rtlpriv
, REG_APS_FSMCO
+ 1, bytetmp
);
713 bytetmp
= rtl_read_byte(rtlpriv
, REG_APS_FSMCO
+ 1);
717 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "reg0xec:%x:%x\n",
718 rtl_read_dword(rtlpriv
, 0xEC), bytetmp
);
720 while ((bytetmp
& BIT(0)) && retry
< 1000) {
723 bytetmp
= rtl_read_byte(rtlpriv
, REG_APS_FSMCO
+ 1);
724 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "reg0xec:%x:%x\n",
725 rtl_read_dword(rtlpriv
, 0xEC), bytetmp
);
729 rtl_write_word(rtlpriv
, REG_APS_FSMCO
, 0x1012);
731 rtl_write_byte(rtlpriv
, REG_SYS_ISO_CTRL
+ 1, 0x82);
734 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
735 bytetmp
= rtl_read_byte(rtlpriv
, REG_AFE_XTAL_CTRL
+2) & 0xfd;
736 rtl_write_byte(rtlpriv
, REG_AFE_XTAL_CTRL
+2, bytetmp
);
739 rtl_write_word(rtlpriv
, REG_CR
, 0x2ff);
741 if (!_rtl92ce_llt_table_init(hw
))
744 rtl_write_dword(rtlpriv
, REG_HISR
, 0xffffffff);
745 rtl_write_byte(rtlpriv
, REG_HISRE
, 0xff);
747 rtl_write_word(rtlpriv
, REG_TRXFF_BNDY
+ 2, 0x27ff);
749 wordtmp
= rtl_read_word(rtlpriv
, REG_TRXDMA_CTRL
);
752 rtl_write_word(rtlpriv
, REG_TRXDMA_CTRL
, wordtmp
);
754 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 1, 0x1F);
755 rtl_write_dword(rtlpriv
, REG_RCR
, rtlpci
->receive_config
);
756 rtl_write_dword(rtlpriv
, REG_TCR
, rtlpci
->transmit_config
);
758 rtl_write_byte(rtlpriv
, 0x4d0, 0x0);
760 rtl_write_dword(rtlpriv
, REG_BCNQ_DESA
,
761 ((u64
) rtlpci
->tx_ring
[BEACON_QUEUE
].dma
) &
763 rtl_write_dword(rtlpriv
, REG_MGQ_DESA
,
764 (u64
) rtlpci
->tx_ring
[MGNT_QUEUE
].dma
&
766 rtl_write_dword(rtlpriv
, REG_VOQ_DESA
,
767 (u64
) rtlpci
->tx_ring
[VO_QUEUE
].dma
& DMA_BIT_MASK(32));
768 rtl_write_dword(rtlpriv
, REG_VIQ_DESA
,
769 (u64
) rtlpci
->tx_ring
[VI_QUEUE
].dma
& DMA_BIT_MASK(32));
770 rtl_write_dword(rtlpriv
, REG_BEQ_DESA
,
771 (u64
) rtlpci
->tx_ring
[BE_QUEUE
].dma
& DMA_BIT_MASK(32));
772 rtl_write_dword(rtlpriv
, REG_BKQ_DESA
,
773 (u64
) rtlpci
->tx_ring
[BK_QUEUE
].dma
& DMA_BIT_MASK(32));
774 rtl_write_dword(rtlpriv
, REG_HQ_DESA
,
775 (u64
) rtlpci
->tx_ring
[HIGH_QUEUE
].dma
&
777 rtl_write_dword(rtlpriv
, REG_RX_DESA
,
778 (u64
) rtlpci
->rx_ring
[RX_MPDU_QUEUE
].dma
&
781 if (IS_92C_SERIAL(rtlhal
->version
))
782 rtl_write_byte(rtlpriv
, REG_PCIE_CTRL_REG
+ 3, 0x77);
784 rtl_write_byte(rtlpriv
, REG_PCIE_CTRL_REG
+ 3, 0x22);
786 rtl_write_dword(rtlpriv
, REG_INT_MIG
, 0);
788 bytetmp
= rtl_read_byte(rtlpriv
, REG_APSD_CTRL
);
789 rtl_write_byte(rtlpriv
, REG_APSD_CTRL
, bytetmp
& ~BIT(6));
792 bytetmp
= rtl_read_byte(rtlpriv
, REG_APSD_CTRL
);
793 } while ((retry
< 200) && (bytetmp
& BIT(7)));
795 _rtl92ce_gen_refresh_led_state(hw
);
797 rtl_write_dword(rtlpriv
, REG_MCUTST_1
, 0x0);
802 static void _rtl92ce_hw_configure(struct ieee80211_hw
*hw
)
804 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
805 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
806 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
810 reg_bw_opmode
= BW_OPMODE_20MHZ
;
811 reg_prsr
= RATE_ALL_CCK
| RATE_ALL_OFDM_AG
;
813 rtl_write_byte(rtlpriv
, REG_INIRTS_RATE_SEL
, 0x8);
815 rtl_write_byte(rtlpriv
, REG_BWOPMODE
, reg_bw_opmode
);
817 rtl_write_dword(rtlpriv
, REG_RRSR
, reg_prsr
);
819 rtl_write_byte(rtlpriv
, REG_SLOT
, 0x09);
821 rtl_write_byte(rtlpriv
, REG_AMPDU_MIN_SPACE
, 0x0);
823 rtl_write_word(rtlpriv
, REG_FWHW_TXQ_CTRL
, 0x1F80);
825 rtl_write_word(rtlpriv
, REG_RL
, 0x0707);
827 rtl_write_dword(rtlpriv
, REG_BAR_MODE_CTRL
, 0x02012802);
829 rtl_write_byte(rtlpriv
, REG_HWSEQ_CTRL
, 0xFF);
831 rtl_write_dword(rtlpriv
, REG_DARFRC
, 0x01000000);
832 rtl_write_dword(rtlpriv
, REG_DARFRC
+ 4, 0x07060504);
833 rtl_write_dword(rtlpriv
, REG_RARFRC
, 0x01000000);
834 rtl_write_dword(rtlpriv
, REG_RARFRC
+ 4, 0x07060504);
836 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
837 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
))
838 rtl_write_dword(rtlpriv
, REG_AGGLEN_LMT
, 0x97427431);
840 rtl_write_dword(rtlpriv
, REG_AGGLEN_LMT
, 0xb972a841);
842 rtl_write_byte(rtlpriv
, REG_ATIMWND
, 0x2);
844 rtl_write_byte(rtlpriv
, REG_BCN_MAX_ERR
, 0xff);
846 rtlpci
->reg_bcn_ctrl_val
= 0x1f;
847 rtl_write_byte(rtlpriv
, REG_BCN_CTRL
, rtlpci
->reg_bcn_ctrl_val
);
849 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0xff);
851 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0xff);
853 rtl_write_byte(rtlpriv
, REG_PIFS
, 0x1C);
854 rtl_write_byte(rtlpriv
, REG_AGGR_BREAK_TIME
, 0x16);
856 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
857 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
)) {
858 rtl_write_word(rtlpriv
, REG_NAV_PROT_LEN
, 0x0020);
859 rtl_write_word(rtlpriv
, REG_PROT_MODE_CTRL
, 0x0402);
861 rtl_write_word(rtlpriv
, REG_NAV_PROT_LEN
, 0x0020);
862 rtl_write_word(rtlpriv
, REG_NAV_PROT_LEN
, 0x0020);
865 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
866 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
))
867 rtl_write_dword(rtlpriv
, REG_FAST_EDCA_CTRL
, 0x03086666);
869 rtl_write_dword(rtlpriv
, REG_FAST_EDCA_CTRL
, 0x086666);
871 rtl_write_byte(rtlpriv
, REG_ACKTO
, 0x40);
873 rtl_write_word(rtlpriv
, REG_SPEC_SIFS
, 0x1010);
874 rtl_write_word(rtlpriv
, REG_MAC_SPEC_SIFS
, 0x1010);
876 rtl_write_word(rtlpriv
, REG_SIFS_CTX
, 0x1010);
878 rtl_write_word(rtlpriv
, REG_SIFS_TRX
, 0x1010);
880 rtl_write_dword(rtlpriv
, REG_MAR
, 0xffffffff);
881 rtl_write_dword(rtlpriv
, REG_MAR
+ 4, 0xffffffff);
885 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw
*hw
)
887 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
888 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
890 rtl_write_byte(rtlpriv
, 0x34b, 0x93);
891 rtl_write_word(rtlpriv
, 0x350, 0x870c);
892 rtl_write_byte(rtlpriv
, 0x352, 0x1);
894 if (ppsc
->support_backdoor
)
895 rtl_write_byte(rtlpriv
, 0x349, 0x1b);
897 rtl_write_byte(rtlpriv
, 0x349, 0x03);
899 rtl_write_word(rtlpriv
, 0x350, 0x2718);
900 rtl_write_byte(rtlpriv
, 0x352, 0x1);
903 void rtl92ce_enable_hw_security_config(struct ieee80211_hw
*hw
)
905 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
908 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
909 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
910 rtlpriv
->sec
.pairwise_enc_algorithm
,
911 rtlpriv
->sec
.group_enc_algorithm
);
913 if (rtlpriv
->cfg
->mod_params
->sw_crypto
|| rtlpriv
->sec
.use_sw_sec
) {
914 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
915 "not open hw encryption\n");
919 sec_reg_value
= SCR_TxEncEnable
| SCR_RxDecEnable
;
921 if (rtlpriv
->sec
.use_defaultkey
) {
922 sec_reg_value
|= SCR_TxUseDK
;
923 sec_reg_value
|= SCR_RxUseDK
;
926 sec_reg_value
|= (SCR_RXBCUSEDK
| SCR_TXBCUSEDK
);
928 rtl_write_byte(rtlpriv
, REG_CR
+ 1, 0x02);
930 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_LOUD
,
931 "The SECR-value %x\n", sec_reg_value
);
933 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_WPA_CONFIG
, &sec_reg_value
);
937 int rtl92ce_hw_init(struct ieee80211_hw
*hw
)
939 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
940 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
941 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
942 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
943 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
944 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
945 bool rtstatus
= true;
951 rtlpci
->being_init_adapter
= true;
953 /* Since this function can take a very long time (up to 350 ms)
954 * and can be called with irqs disabled, reenable the irqs
955 * to let the other devices continue being serviced.
957 * It is safe doing so since our own interrupts will only be enabled
958 * in a subsequent step.
960 local_save_flags(flags
);
963 rtlhal
->fw_ready
= false;
964 rtlpriv
->intf_ops
->disable_aspm(hw
);
965 rtstatus
= _rtl92ce_init_mac(hw
);
967 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "Init MAC failed\n");
972 err
= rtl92c_download_fw(hw
);
974 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
975 "Failed to download FW. Init HW without FW now..\n");
980 rtlhal
->fw_ready
= true;
981 rtlhal
->last_hmeboxnum
= 0;
982 rtl92c_phy_mac_config(hw
);
983 /* because last function modify RCR, so we update
984 * rcr var here, or TP will unstable for receive_config
985 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
986 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
987 rtlpci
->receive_config
= rtl_read_dword(rtlpriv
, REG_RCR
);
988 rtlpci
->receive_config
&= ~(RCR_ACRC32
| RCR_AICV
);
989 rtl_write_dword(rtlpriv
, REG_RCR
, rtlpci
->receive_config
);
990 rtl92c_phy_bb_config(hw
);
991 rtlphy
->rf_mode
= RF_OP_BY_SW_3WIRE
;
992 rtl92c_phy_rf_config(hw
);
993 if (IS_VENDOR_UMC_A_CUT(rtlhal
->version
) &&
994 !IS_92C_SERIAL(rtlhal
->version
)) {
995 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_RX_G1
, MASKDWORD
, 0x30255);
996 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_RX_G2
, MASKDWORD
, 0x50a00);
997 } else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal
->version
)) {
998 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x0C, MASKDWORD
, 0x894AE);
999 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x0A, MASKDWORD
, 0x1AF31);
1000 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_IPA
, MASKDWORD
, 0x8F425);
1001 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_SYN_G2
, MASKDWORD
, 0x4F200);
1002 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_RCK1
, MASKDWORD
, 0x44053);
1003 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_RCK2
, MASKDWORD
, 0x80201);
1005 rtlphy
->rfreg_chnlval
[0] = rtl_get_rfreg(hw
, (enum radio_path
)0,
1006 RF_CHNLBW
, RFREG_OFFSET_MASK
);
1007 rtlphy
->rfreg_chnlval
[1] = rtl_get_rfreg(hw
, (enum radio_path
)1,
1008 RF_CHNLBW
, RFREG_OFFSET_MASK
);
1009 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BCCKEN
, 0x1);
1010 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BOFDMEN
, 0x1);
1011 rtl_set_bbreg(hw
, RFPGA0_ANALOGPARAMETER2
, BIT(10), 1);
1012 _rtl92ce_hw_configure(hw
);
1013 rtl_cam_reset_all_entry(hw
);
1014 rtl92ce_enable_hw_security_config(hw
);
1016 ppsc
->rfpwr_state
= ERFON
;
1018 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_ETHER_ADDR
, mac
->mac_addr
);
1019 _rtl92ce_enable_aspm_back_door(hw
);
1020 rtlpriv
->intf_ops
->enable_aspm(hw
);
1022 rtl8192ce_bt_hw_init(hw
);
1024 if (ppsc
->rfpwr_state
== ERFON
) {
1025 rtl92c_phy_set_rfpath_switch(hw
, 1);
1026 if (rtlphy
->iqk_initialized
) {
1027 rtl92c_phy_iq_calibrate(hw
, true);
1029 rtl92c_phy_iq_calibrate(hw
, false);
1030 rtlphy
->iqk_initialized
= true;
1033 rtl92c_dm_check_txpower_tracking(hw
);
1034 rtl92c_phy_lc_calibrate(hw
);
1037 is92c
= IS_92C_SERIAL(rtlhal
->version
);
1038 tmp_u1b
= efuse_read_1byte(hw
, 0x1FA);
1039 if (!(tmp_u1b
& BIT(0))) {
1040 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x15, 0x0F, 0x05);
1041 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "PA BIAS path A\n");
1044 if (!(tmp_u1b
& BIT(1)) && is92c
) {
1045 rtl_set_rfreg(hw
, RF90_PATH_B
, 0x15, 0x0F, 0x05);
1046 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "PA BIAS path B\n");
1049 if (!(tmp_u1b
& BIT(4))) {
1050 tmp_u1b
= rtl_read_byte(rtlpriv
, 0x16);
1052 rtl_write_byte(rtlpriv
, 0x16, tmp_u1b
| 0x80);
1054 rtl_write_byte(rtlpriv
, 0x16, tmp_u1b
| 0x90);
1055 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "under 1.5V\n");
1059 local_irq_restore(flags
);
1060 rtlpci
->being_init_adapter
= false;
1064 static enum version_8192c
_rtl92ce_read_chip_version(struct ieee80211_hw
*hw
)
1066 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1067 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1068 enum version_8192c version
= VERSION_UNKNOWN
;
1070 const char *versionid
;
1072 value32
= rtl_read_dword(rtlpriv
, REG_SYS_CFG
);
1073 if (value32
& TRP_VAUX_EN
) {
1074 version
= (value32
& TYPE_ID
) ? VERSION_A_CHIP_92C
:
1077 version
= (enum version_8192c
) (CHIP_VER_B
|
1078 ((value32
& TYPE_ID
) ? CHIP_92C_BITMASK
: 0) |
1079 ((value32
& VENDOR_ID
) ? CHIP_VENDOR_UMC
: 0));
1080 if ((!IS_CHIP_VENDOR_UMC(version
)) && (value32
&
1081 CHIP_VER_RTL_MASK
)) {
1082 version
= (enum version_8192c
)(version
|
1083 ((((value32
& CHIP_VER_RTL_MASK
) == BIT(12))
1084 ? CHIP_VENDOR_UMC_B_CUT
: CHIP_UNKNOWN
) |
1087 if (IS_92C_SERIAL(version
)) {
1088 value32
= rtl_read_dword(rtlpriv
, REG_HPON_FSM
);
1089 version
= (enum version_8192c
)(version
|
1090 ((CHIP_BONDING_IDENTIFIER(value32
)
1091 == CHIP_BONDING_92C_1T2R
) ?
1097 case VERSION_B_CHIP_92C
:
1098 versionid
= "B_CHIP_92C";
1100 case VERSION_B_CHIP_88C
:
1101 versionid
= "B_CHIP_88C";
1103 case VERSION_A_CHIP_92C
:
1104 versionid
= "A_CHIP_92C";
1106 case VERSION_A_CHIP_88C
:
1107 versionid
= "A_CHIP_88C";
1109 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT
:
1110 versionid
= "A_CUT_92C_1T2R";
1112 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT
:
1113 versionid
= "A_CUT_92C";
1115 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT
:
1116 versionid
= "A_CUT_88C";
1118 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT
:
1119 versionid
= "B_CUT_92C_1T2R";
1121 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT
:
1122 versionid
= "B_CUT_92C";
1124 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT
:
1125 versionid
= "B_CUT_88C";
1128 versionid
= "Unknown. Bug?";
1132 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_EMERG
,
1133 "Chip Version ID: %s\n", versionid
);
1135 switch (version
& 0x3) {
1137 rtlphy
->rf_type
= RF_1T1R
;
1140 rtlphy
->rf_type
= RF_2T2R
;
1143 rtlphy
->rf_type
= RF_1T2R
;
1146 rtlphy
->rf_type
= RF_1T1R
;
1147 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1148 "ERROR RF_Type is set!!\n");
1152 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Chip RF Type: %s\n",
1153 rtlphy
->rf_type
== RF_2T2R
? "RF_2T2R" : "RF_1T1R");
1158 static int _rtl92ce_set_media_status(struct ieee80211_hw
*hw
,
1159 enum nl80211_iftype type
)
1161 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1162 u8 bt_msr
= rtl_read_byte(rtlpriv
, MSR
);
1163 enum led_ctl_mode ledaction
= LED_CTL_NO_LINK
;
1164 u8 mode
= MSR_NOLINK
;
1169 case NL80211_IFTYPE_UNSPECIFIED
:
1171 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1172 "Set Network type to NO LINK!\n");
1174 case NL80211_IFTYPE_ADHOC
:
1176 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1177 "Set Network type to Ad Hoc!\n");
1179 case NL80211_IFTYPE_STATION
:
1181 ledaction
= LED_CTL_LINK
;
1182 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1183 "Set Network type to STA!\n");
1185 case NL80211_IFTYPE_AP
:
1187 ledaction
= LED_CTL_LINK
;
1188 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1189 "Set Network type to AP!\n");
1191 case NL80211_IFTYPE_MESH_POINT
:
1193 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1194 "Set Network type to Mesh Point!\n");
1197 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1198 "Network type %d not supported!\n", type
);
1203 /* MSR_INFRA == Link in infrastructure network;
1204 * MSR_ADHOC == Link in ad hoc network;
1205 * Therefore, check link state is necessary.
1207 * MSR_AP == AP mode; link state does not matter here.
1209 if (mode
!= MSR_AP
&&
1210 rtlpriv
->mac80211
.link_state
< MAC80211_LINKED
) {
1212 ledaction
= LED_CTL_NO_LINK
;
1214 if (mode
== MSR_NOLINK
|| mode
== MSR_INFRA
) {
1215 _rtl92ce_stop_tx_beacon(hw
);
1216 _rtl92ce_enable_bcn_sub_func(hw
);
1217 } else if (mode
== MSR_ADHOC
|| mode
== MSR_AP
) {
1218 _rtl92ce_resume_tx_beacon(hw
);
1219 _rtl92ce_disable_bcn_sub_func(hw
);
1221 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
1222 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1225 rtl_write_byte(rtlpriv
, MSR
, bt_msr
| mode
);
1227 rtlpriv
->cfg
->ops
->led_control(hw
, ledaction
);
1229 rtl_write_byte(rtlpriv
, REG_BCNTCFG
+ 1, 0x00);
1231 rtl_write_byte(rtlpriv
, REG_BCNTCFG
+ 1, 0x66);
1235 void rtl92ce_set_check_bssid(struct ieee80211_hw
*hw
, bool check_bssid
)
1237 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1240 if (rtlpriv
->psc
.rfpwr_state
!= ERFON
)
1243 rtlpriv
->cfg
->ops
->get_hw_reg(hw
, HW_VAR_RCR
, (u8
*)(®_rcr
));
1246 reg_rcr
|= (RCR_CBSSID_DATA
| RCR_CBSSID_BCN
);
1247 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_RCR
,
1249 _rtl92ce_set_bcn_ctrl_reg(hw
, 0, BIT(4));
1250 } else if (!check_bssid
) {
1251 reg_rcr
&= (~(RCR_CBSSID_DATA
| RCR_CBSSID_BCN
));
1252 _rtl92ce_set_bcn_ctrl_reg(hw
, BIT(4), 0);
1253 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
1254 HW_VAR_RCR
, (u8
*) (®_rcr
));
1259 int rtl92ce_set_network_type(struct ieee80211_hw
*hw
, enum nl80211_iftype type
)
1261 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1263 if (_rtl92ce_set_media_status(hw
, type
))
1266 if (rtlpriv
->mac80211
.link_state
== MAC80211_LINKED
) {
1267 if (type
!= NL80211_IFTYPE_AP
&&
1268 type
!= NL80211_IFTYPE_MESH_POINT
)
1269 rtl92ce_set_check_bssid(hw
, true);
1271 rtl92ce_set_check_bssid(hw
, false);
1277 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1278 void rtl92ce_set_qos(struct ieee80211_hw
*hw
, int aci
)
1280 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1281 rtl92c_dm_init_edca_turbo(hw
);
1284 rtl_write_dword(rtlpriv
, REG_EDCA_BK_PARAM
, 0xa44f);
1287 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1290 rtl_write_dword(rtlpriv
, REG_EDCA_VI_PARAM
, 0x5e4322);
1293 rtl_write_dword(rtlpriv
, REG_EDCA_VO_PARAM
, 0x2f3222);
1296 RT_ASSERT(false, "invalid aci: %d !\n", aci
);
1301 void rtl92ce_enable_interrupt(struct ieee80211_hw
*hw
)
1303 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1304 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1306 rtl_write_dword(rtlpriv
, REG_HIMR
, rtlpci
->irq_mask
[0] & 0xFFFFFFFF);
1307 rtl_write_dword(rtlpriv
, REG_HIMRE
, rtlpci
->irq_mask
[1] & 0xFFFFFFFF);
1308 rtlpci
->irq_enabled
= true;
1311 void rtl92ce_disable_interrupt(struct ieee80211_hw
*hw
)
1313 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1314 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1316 rtl_write_dword(rtlpriv
, REG_HIMR
, IMR8190_DISABLED
);
1317 rtl_write_dword(rtlpriv
, REG_HIMRE
, IMR8190_DISABLED
);
1318 rtlpci
->irq_enabled
= false;
1321 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw
*hw
)
1323 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1324 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
1325 struct rtl_hal
*rtlhal
= rtl_hal(rtlpriv
);
1329 rtlpriv
->intf_ops
->enable_aspm(hw
);
1330 rtl_write_byte(rtlpriv
, REG_TXPAUSE
, 0xFF);
1331 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x00, RFREG_OFFSET_MASK
, 0x00);
1332 rtl_write_byte(rtlpriv
, REG_RF_CTRL
, 0x00);
1333 rtl_write_byte(rtlpriv
, REG_APSD_CTRL
, 0x40);
1334 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
, 0xE2);
1335 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
, 0xE0);
1336 if (rtl_read_byte(rtlpriv
, REG_MCUFWDL
) & BIT(7))
1337 rtl92c_firmware_selfreset(hw
);
1338 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
+ 1, 0x51);
1339 rtl_write_byte(rtlpriv
, REG_MCUFWDL
, 0x00);
1340 rtl_write_dword(rtlpriv
, REG_GPIO_PIN_CTRL
, 0x00000000);
1341 u1b_tmp
= rtl_read_byte(rtlpriv
, REG_GPIO_PIN_CTRL
);
1342 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
1343 ((rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
) ||
1344 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC8
))) {
1345 rtl_write_dword(rtlpriv
, REG_GPIO_PIN_CTRL
, 0x00F30000 |
1348 rtl_write_dword(rtlpriv
, REG_GPIO_PIN_CTRL
, 0x00FF0000 |
1351 rtl_write_word(rtlpriv
, REG_GPIO_IO_SEL
, 0x0790);
1352 rtl_write_word(rtlpriv
, REG_LEDCFG0
, 0x8080);
1353 rtl_write_byte(rtlpriv
, REG_AFE_PLL_CTRL
, 0x80);
1354 if (!IS_81XXC_VENDOR_UMC_B_CUT(rtlhal
->version
))
1355 rtl_write_byte(rtlpriv
, REG_SPS0_CTRL
, 0x23);
1356 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
1357 u4b_tmp
= rtl_read_dword(rtlpriv
, REG_AFE_XTAL_CTRL
);
1358 u4b_tmp
|= 0x03824800;
1359 rtl_write_dword(rtlpriv
, REG_AFE_XTAL_CTRL
, u4b_tmp
);
1361 rtl_write_dword(rtlpriv
, REG_AFE_XTAL_CTRL
, 0x0e);
1364 rtl_write_byte(rtlpriv
, REG_RSV_CTRL
, 0x0e);
1365 rtl_write_byte(rtlpriv
, REG_APS_FSMCO
+ 1, 0x10);
1368 void rtl92ce_card_disable(struct ieee80211_hw
*hw
)
1370 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1371 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
1372 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1373 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1374 enum nl80211_iftype opmode
;
1376 mac
->link_state
= MAC80211_NOLINK
;
1377 opmode
= NL80211_IFTYPE_UNSPECIFIED
;
1378 _rtl92ce_set_media_status(hw
, opmode
);
1379 if (rtlpci
->driver_is_goingto_unload
||
1380 ppsc
->rfoff_reason
> RF_CHANGE_BY_PS
)
1381 rtlpriv
->cfg
->ops
->led_control(hw
, LED_CTL_POWER_OFF
);
1382 RT_SET_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
);
1383 _rtl92ce_poweroff_adapter(hw
);
1385 /* after power off we should do iqk again */
1386 rtlpriv
->phy
.iqk_initialized
= false;
1389 void rtl92ce_interrupt_recognized(struct ieee80211_hw
*hw
,
1390 u32
*p_inta
, u32
*p_intb
)
1392 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1393 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1395 *p_inta
= rtl_read_dword(rtlpriv
, ISR
) & rtlpci
->irq_mask
[0];
1396 rtl_write_dword(rtlpriv
, ISR
, *p_inta
);
1399 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1400 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1404 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw
*hw
)
1407 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1408 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1409 u16 bcn_interval
, atim_window
;
1411 bcn_interval
= mac
->beacon_interval
;
1412 atim_window
= 2; /*FIX MERGE */
1413 rtl92ce_disable_interrupt(hw
);
1414 rtl_write_word(rtlpriv
, REG_ATIMWND
, atim_window
);
1415 rtl_write_word(rtlpriv
, REG_BCN_INTERVAL
, bcn_interval
);
1416 rtl_write_word(rtlpriv
, REG_BCNTCFG
, 0x660f);
1417 rtl_write_byte(rtlpriv
, REG_RXTSF_OFFSET_CCK
, 0x18);
1418 rtl_write_byte(rtlpriv
, REG_RXTSF_OFFSET_OFDM
, 0x18);
1419 rtl_write_byte(rtlpriv
, 0x606, 0x30);
1420 rtl92ce_enable_interrupt(hw
);
1423 void rtl92ce_set_beacon_interval(struct ieee80211_hw
*hw
)
1425 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1426 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1427 u16 bcn_interval
= mac
->beacon_interval
;
1429 RT_TRACE(rtlpriv
, COMP_BEACON
, DBG_DMESG
,
1430 "beacon_interval:%d\n", bcn_interval
);
1431 rtl92ce_disable_interrupt(hw
);
1432 rtl_write_word(rtlpriv
, REG_BCN_INTERVAL
, bcn_interval
);
1433 rtl92ce_enable_interrupt(hw
);
1436 void rtl92ce_update_interrupt_mask(struct ieee80211_hw
*hw
,
1437 u32 add_msr
, u32 rm_msr
)
1439 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1440 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1442 RT_TRACE(rtlpriv
, COMP_INTR
, DBG_LOUD
, "add_msr:%x, rm_msr:%x\n",
1446 rtlpci
->irq_mask
[0] |= add_msr
;
1448 rtlpci
->irq_mask
[0] &= (~rm_msr
);
1449 rtl92ce_disable_interrupt(hw
);
1450 rtl92ce_enable_interrupt(hw
);
1453 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw
*hw
,
1457 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1458 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1459 u8 rf_path
, index
, tempval
;
1462 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1463 for (i
= 0; i
< 3; i
++) {
1464 if (!autoload_fail
) {
1466 eeprom_chnlarea_txpwr_cck
[rf_path
][i
] =
1467 hwinfo
[EEPROM_TXPOWERCCK
+ rf_path
* 3 + i
];
1469 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][i
] =
1470 hwinfo
[EEPROM_TXPOWERHT40_1S
+ rf_path
* 3 +
1474 eeprom_chnlarea_txpwr_cck
[rf_path
][i
] =
1475 EEPROM_DEFAULT_TXPOWERLEVEL
;
1477 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][i
] =
1478 EEPROM_DEFAULT_TXPOWERLEVEL
;
1483 for (i
= 0; i
< 3; i
++) {
1485 tempval
= hwinfo
[EEPROM_TXPOWERHT40_2SDIFF
+ i
];
1487 tempval
= EEPROM_DEFAULT_HT40_2SDIFF
;
1488 rtlefuse
->eprom_chnl_txpwr_ht40_2sdf
[RF90_PATH_A
][i
] =
1490 rtlefuse
->eprom_chnl_txpwr_ht40_2sdf
[RF90_PATH_B
][i
] =
1491 ((tempval
& 0xf0) >> 4);
1494 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1495 for (i
= 0; i
< 3; i
++)
1496 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1497 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1500 eeprom_chnlarea_txpwr_cck
[rf_path
][i
]);
1501 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1502 for (i
= 0; i
< 3; i
++)
1503 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1504 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1507 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][i
]);
1508 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1509 for (i
= 0; i
< 3; i
++)
1510 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1511 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1514 eprom_chnl_txpwr_ht40_2sdf
[rf_path
][i
]);
1516 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1517 for (i
= 0; i
< 14; i
++) {
1518 index
= rtl92c_get_chnl_group((u8
)i
);
1520 rtlefuse
->txpwrlevel_cck
[rf_path
][i
] =
1521 rtlefuse
->eeprom_chnlarea_txpwr_cck
[rf_path
][index
];
1522 rtlefuse
->txpwrlevel_ht40_1s
[rf_path
][i
] =
1524 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][index
];
1527 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][index
] -
1529 eprom_chnl_txpwr_ht40_2sdf
[rf_path
][index
])
1531 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
] =
1533 eeprom_chnlarea_txpwr_ht40_1s
[rf_path
]
1536 eprom_chnl_txpwr_ht40_2sdf
[rf_path
]
1539 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
] = 0;
1543 for (i
= 0; i
< 14; i
++) {
1544 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1545 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1547 rtlefuse
->txpwrlevel_cck
[rf_path
][i
],
1548 rtlefuse
->txpwrlevel_ht40_1s
[rf_path
][i
],
1549 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
]);
1553 for (i
= 0; i
< 3; i
++) {
1554 if (!autoload_fail
) {
1555 rtlefuse
->eeprom_pwrlimit_ht40
[i
] =
1556 hwinfo
[EEPROM_TXPWR_GROUP
+ i
];
1557 rtlefuse
->eeprom_pwrlimit_ht20
[i
] =
1558 hwinfo
[EEPROM_TXPWR_GROUP
+ 3 + i
];
1560 rtlefuse
->eeprom_pwrlimit_ht40
[i
] = 0;
1561 rtlefuse
->eeprom_pwrlimit_ht20
[i
] = 0;
1565 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1566 for (i
= 0; i
< 14; i
++) {
1567 index
= rtl92c_get_chnl_group((u8
)i
);
1569 if (rf_path
== RF90_PATH_A
) {
1570 rtlefuse
->pwrgroup_ht20
[rf_path
][i
] =
1571 (rtlefuse
->eeprom_pwrlimit_ht20
[index
]
1573 rtlefuse
->pwrgroup_ht40
[rf_path
][i
] =
1574 (rtlefuse
->eeprom_pwrlimit_ht40
[index
]
1576 } else if (rf_path
== RF90_PATH_B
) {
1577 rtlefuse
->pwrgroup_ht20
[rf_path
][i
] =
1578 ((rtlefuse
->eeprom_pwrlimit_ht20
[index
]
1580 rtlefuse
->pwrgroup_ht40
[rf_path
][i
] =
1581 ((rtlefuse
->eeprom_pwrlimit_ht40
[index
]
1585 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1586 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1588 rtlefuse
->pwrgroup_ht20
[rf_path
][i
]);
1589 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1590 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1592 rtlefuse
->pwrgroup_ht40
[rf_path
][i
]);
1596 for (i
= 0; i
< 14; i
++) {
1597 index
= rtl92c_get_chnl_group((u8
)i
);
1600 tempval
= hwinfo
[EEPROM_TXPOWERHT20DIFF
+ index
];
1602 tempval
= EEPROM_DEFAULT_HT20_DIFF
;
1604 rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
] = (tempval
& 0xF);
1605 rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
] =
1606 ((tempval
>> 4) & 0xF);
1608 if (rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
] & BIT(3))
1609 rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
] |= 0xF0;
1611 if (rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
] & BIT(3))
1612 rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
] |= 0xF0;
1614 index
= rtl92c_get_chnl_group((u8
)i
);
1617 tempval
= hwinfo
[EEPROM_TXPOWER_OFDMDIFF
+ index
];
1619 tempval
= EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF
;
1621 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][i
] = (tempval
& 0xF);
1622 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_B
][i
] =
1623 ((tempval
>> 4) & 0xF);
1626 rtlefuse
->legacy_ht_txpowerdiff
=
1627 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][7];
1629 for (i
= 0; i
< 14; i
++)
1630 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1631 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1632 i
, rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
]);
1633 for (i
= 0; i
< 14; i
++)
1634 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1635 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1636 i
, rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][i
]);
1637 for (i
= 0; i
< 14; i
++)
1638 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1639 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1640 i
, rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
]);
1641 for (i
= 0; i
< 14; i
++)
1642 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1643 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1644 i
, rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_B
][i
]);
1647 rtlefuse
->eeprom_regulatory
= (hwinfo
[RF_OPTION1
] & 0x7);
1649 rtlefuse
->eeprom_regulatory
= 0;
1650 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1651 "eeprom_regulatory = 0x%x\n", rtlefuse
->eeprom_regulatory
);
1653 if (!autoload_fail
) {
1654 rtlefuse
->eeprom_tssi
[RF90_PATH_A
] = hwinfo
[EEPROM_TSSI_A
];
1655 rtlefuse
->eeprom_tssi
[RF90_PATH_B
] = hwinfo
[EEPROM_TSSI_B
];
1657 rtlefuse
->eeprom_tssi
[RF90_PATH_A
] = EEPROM_DEFAULT_TSSI
;
1658 rtlefuse
->eeprom_tssi
[RF90_PATH_B
] = EEPROM_DEFAULT_TSSI
;
1660 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1661 rtlefuse
->eeprom_tssi
[RF90_PATH_A
],
1662 rtlefuse
->eeprom_tssi
[RF90_PATH_B
]);
1665 tempval
= hwinfo
[EEPROM_THERMAL_METER
];
1667 tempval
= EEPROM_DEFAULT_THERMALMETER
;
1668 rtlefuse
->eeprom_thermalmeter
= (tempval
& 0x1f);
1670 if (rtlefuse
->eeprom_thermalmeter
== 0x1f || autoload_fail
)
1671 rtlefuse
->apk_thermalmeterignore
= true;
1673 rtlefuse
->thermalmeter
[0] = rtlefuse
->eeprom_thermalmeter
;
1674 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1675 "thermalmeter = 0x%x\n", rtlefuse
->eeprom_thermalmeter
);
1678 static void _rtl92ce_read_adapter_info(struct ieee80211_hw
*hw
)
1680 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1681 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1682 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1684 u8 hwinfo
[HWSET_MAX_SIZE
];
1687 if (rtlefuse
->epromtype
== EEPROM_BOOT_EFUSE
) {
1688 rtl_efuse_shadow_map_update(hw
);
1690 memcpy((void *)hwinfo
,
1691 (void *)&rtlefuse
->efuse_map
[EFUSE_INIT_MAP
][0],
1693 } else if (rtlefuse
->epromtype
== EEPROM_93C46
) {
1694 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1695 "RTL819X Not boot from eeprom, check it !!");
1698 RT_PRINT_DATA(rtlpriv
, COMP_INIT
, DBG_DMESG
, "MAP",
1699 hwinfo
, HWSET_MAX_SIZE
);
1701 eeprom_id
= *((u16
*)&hwinfo
[0]);
1702 if (eeprom_id
!= RTL8190_EEPROM_ID
) {
1703 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
1704 "EEPROM ID(%#x) is invalid!!\n", eeprom_id
);
1705 rtlefuse
->autoload_failflag
= true;
1707 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Autoload OK\n");
1708 rtlefuse
->autoload_failflag
= false;
1711 if (rtlefuse
->autoload_failflag
)
1714 rtlefuse
->eeprom_vid
= *(u16
*)&hwinfo
[EEPROM_VID
];
1715 rtlefuse
->eeprom_did
= *(u16
*)&hwinfo
[EEPROM_DID
];
1716 rtlefuse
->eeprom_svid
= *(u16
*)&hwinfo
[EEPROM_SVID
];
1717 rtlefuse
->eeprom_smid
= *(u16
*)&hwinfo
[EEPROM_SMID
];
1718 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1719 "EEPROMId = 0x%4x\n", eeprom_id
);
1720 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1721 "EEPROM VID = 0x%4x\n", rtlefuse
->eeprom_vid
);
1722 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1723 "EEPROM DID = 0x%4x\n", rtlefuse
->eeprom_did
);
1724 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1725 "EEPROM SVID = 0x%4x\n", rtlefuse
->eeprom_svid
);
1726 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1727 "EEPROM SMID = 0x%4x\n", rtlefuse
->eeprom_smid
);
1729 for (i
= 0; i
< 6; i
+= 2) {
1730 usvalue
= *(u16
*)&hwinfo
[EEPROM_MAC_ADDR
+ i
];
1731 *((u16
*) (&rtlefuse
->dev_addr
[i
])) = usvalue
;
1734 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "%pM\n", rtlefuse
->dev_addr
);
1736 _rtl92ce_read_txpower_info_from_hwpg(hw
,
1737 rtlefuse
->autoload_failflag
,
1740 rtl8192ce_read_bt_coexist_info_from_hwpg(hw
,
1741 rtlefuse
->autoload_failflag
,
1744 rtlefuse
->eeprom_channelplan
= *&hwinfo
[EEPROM_CHANNELPLAN
];
1745 rtlefuse
->eeprom_version
= *(u16
*)&hwinfo
[EEPROM_VERSION
];
1746 rtlefuse
->txpwr_fromeprom
= true;
1747 rtlefuse
->eeprom_oemid
= *&hwinfo
[EEPROM_CUSTOMER_ID
];
1749 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1750 "EEPROM Customer ID: 0x%2x\n", rtlefuse
->eeprom_oemid
);
1752 /* set channel paln to world wide 13 */
1753 rtlefuse
->channel_plan
= COUNTRY_CODE_WORLD_WIDE_13
;
1755 if (rtlhal
->oem_id
== RT_CID_DEFAULT
) {
1756 switch (rtlefuse
->eeprom_oemid
) {
1757 case EEPROM_CID_DEFAULT
:
1758 if (rtlefuse
->eeprom_did
== 0x8176) {
1759 if ((rtlefuse
->eeprom_svid
== 0x103C &&
1760 rtlefuse
->eeprom_smid
== 0x1629))
1761 rtlhal
->oem_id
= RT_CID_819X_HP
;
1763 rtlhal
->oem_id
= RT_CID_DEFAULT
;
1765 rtlhal
->oem_id
= RT_CID_DEFAULT
;
1768 case EEPROM_CID_TOSHIBA
:
1769 rtlhal
->oem_id
= RT_CID_TOSHIBA
;
1771 case EEPROM_CID_QMI
:
1772 rtlhal
->oem_id
= RT_CID_819X_QMI
;
1774 case EEPROM_CID_WHQL
:
1776 rtlhal
->oem_id
= RT_CID_DEFAULT
;
1784 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw
*hw
)
1786 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1787 struct rtl_pci_priv
*pcipriv
= rtl_pcipriv(hw
);
1788 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1790 switch (rtlhal
->oem_id
) {
1791 case RT_CID_819X_HP
:
1792 pcipriv
->ledctl
.led_opendrain
= true;
1794 case RT_CID_819X_LENOVO
:
1795 case RT_CID_DEFAULT
:
1796 case RT_CID_TOSHIBA
:
1798 case RT_CID_819X_ACER
:
1803 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
,
1804 "RT Customized ID: 0x%02X\n", rtlhal
->oem_id
);
1807 void rtl92ce_read_eeprom_info(struct ieee80211_hw
*hw
)
1809 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1810 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1811 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1812 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1815 rtlhal
->version
= _rtl92ce_read_chip_version(hw
);
1816 if (get_rf_type(rtlphy
) == RF_1T1R
)
1817 rtlpriv
->dm
.rfpath_rxenable
[0] = true;
1819 rtlpriv
->dm
.rfpath_rxenable
[0] =
1820 rtlpriv
->dm
.rfpath_rxenable
[1] = true;
1821 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "VersionID = 0x%4x\n",
1823 tmp_u1b
= rtl_read_byte(rtlpriv
, REG_9346CR
);
1824 if (tmp_u1b
& BIT(4)) {
1825 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "Boot from EEPROM\n");
1826 rtlefuse
->epromtype
= EEPROM_93C46
;
1828 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "Boot from EFUSE\n");
1829 rtlefuse
->epromtype
= EEPROM_BOOT_EFUSE
;
1831 if (tmp_u1b
& BIT(5)) {
1832 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Autoload OK\n");
1833 rtlefuse
->autoload_failflag
= false;
1834 _rtl92ce_read_adapter_info(hw
);
1836 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "Autoload ERR!!\n");
1838 _rtl92ce_hal_customized_behavior(hw
);
1841 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw
*hw
,
1842 struct ieee80211_sta
*sta
)
1844 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1845 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
1846 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1847 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1848 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1851 u8 nmode
= mac
->ht_enable
;
1854 u8 curtxbw_40mhz
= mac
->bw_40
;
1855 u8 curshortgi_40mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_40
) ?
1857 u8 curshortgi_20mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_20
) ?
1859 enum wireless_mode wirelessmode
= mac
->mode
;
1862 if (rtlhal
->current_bandtype
== BAND_ON_5G
)
1863 ratr_value
= sta
->supp_rates
[1] << 4;
1865 ratr_value
= sta
->supp_rates
[0];
1866 if (mac
->opmode
== NL80211_IFTYPE_ADHOC
)
1869 ratr_value
|= (sta
->ht_cap
.mcs
.rx_mask
[1] << 20 |
1870 sta
->ht_cap
.mcs
.rx_mask
[0] << 12);
1871 switch (wirelessmode
) {
1872 case WIRELESS_MODE_B
:
1873 if (ratr_value
& 0x0000000c)
1874 ratr_value
&= 0x0000000d;
1876 ratr_value
&= 0x0000000f;
1878 case WIRELESS_MODE_G
:
1879 ratr_value
&= 0x00000FF5;
1881 case WIRELESS_MODE_N_24G
:
1882 case WIRELESS_MODE_N_5G
:
1884 if (get_rf_type(rtlphy
) == RF_1T2R
||
1885 get_rf_type(rtlphy
) == RF_1T1R
)
1886 ratr_mask
= 0x000ff005;
1888 ratr_mask
= 0x0f0ff005;
1890 ratr_value
&= ratr_mask
;
1893 if (rtlphy
->rf_type
== RF_1T2R
)
1894 ratr_value
&= 0x000ff0ff;
1896 ratr_value
&= 0x0f0ff0ff;
1901 if ((rtlpcipriv
->bt_coexist
.bt_coexistence
) &&
1902 (rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
) &&
1903 (rtlpcipriv
->bt_coexist
.bt_cur_state
) &&
1904 (rtlpcipriv
->bt_coexist
.bt_ant_isolation
) &&
1905 ((rtlpcipriv
->bt_coexist
.bt_service
== BT_SCO
) ||
1906 (rtlpcipriv
->bt_coexist
.bt_service
== BT_BUSY
)))
1907 ratr_value
&= 0x0fffcfc0;
1909 ratr_value
&= 0x0FFFFFFF;
1911 if (nmode
&& ((curtxbw_40mhz
&&
1912 curshortgi_40mhz
) || (!curtxbw_40mhz
&&
1913 curshortgi_20mhz
))) {
1915 ratr_value
|= 0x10000000;
1916 tmp_ratr_value
= (ratr_value
>> 12);
1918 for (shortgi_rate
= 15; shortgi_rate
> 0; shortgi_rate
--) {
1919 if ((1 << shortgi_rate
) & tmp_ratr_value
)
1923 shortgi_rate
= (shortgi_rate
<< 12) | (shortgi_rate
<< 8) |
1924 (shortgi_rate
<< 4) | (shortgi_rate
);
1927 rtl_write_dword(rtlpriv
, REG_ARFR0
+ ratr_index
* 4, ratr_value
);
1929 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_DMESG
, "%x\n",
1930 rtl_read_dword(rtlpriv
, REG_ARFR0
));
1933 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw
*hw
,
1934 struct ieee80211_sta
*sta
, u8 rssi_level
)
1936 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1937 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1938 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1939 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1940 struct rtl_sta_info
*sta_entry
= NULL
;
1943 u8 curtxbw_40mhz
= (sta
->ht_cap
.cap
&
1944 IEEE80211_HT_CAP_SUP_WIDTH_20_40
) ? 1 : 0;
1945 u8 curshortgi_40mhz
= (sta
->ht_cap
.cap
&
1946 IEEE80211_HT_CAP_SGI_40
) ? 1 : 0;
1947 u8 curshortgi_20mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_20
) ?
1949 enum wireless_mode wirelessmode
= 0;
1950 bool shortgi
= false;
1954 sta_entry
= (struct rtl_sta_info
*) sta
->drv_priv
;
1955 wirelessmode
= sta_entry
->wireless_mode
;
1956 if (mac
->opmode
== NL80211_IFTYPE_STATION
||
1957 mac
->opmode
== NL80211_IFTYPE_MESH_POINT
)
1958 curtxbw_40mhz
= mac
->bw_40
;
1959 else if (mac
->opmode
== NL80211_IFTYPE_AP
||
1960 mac
->opmode
== NL80211_IFTYPE_ADHOC
)
1961 macid
= sta
->aid
+ 1;
1963 if (rtlhal
->current_bandtype
== BAND_ON_5G
)
1964 ratr_bitmap
= sta
->supp_rates
[1] << 4;
1966 ratr_bitmap
= sta
->supp_rates
[0];
1967 if (mac
->opmode
== NL80211_IFTYPE_ADHOC
)
1968 ratr_bitmap
= 0xfff;
1969 ratr_bitmap
|= (sta
->ht_cap
.mcs
.rx_mask
[1] << 20 |
1970 sta
->ht_cap
.mcs
.rx_mask
[0] << 12);
1971 switch (wirelessmode
) {
1972 case WIRELESS_MODE_B
:
1973 ratr_index
= RATR_INX_WIRELESS_B
;
1974 if (ratr_bitmap
& 0x0000000c)
1975 ratr_bitmap
&= 0x0000000d;
1977 ratr_bitmap
&= 0x0000000f;
1979 case WIRELESS_MODE_G
:
1980 ratr_index
= RATR_INX_WIRELESS_GB
;
1982 if (rssi_level
== 1)
1983 ratr_bitmap
&= 0x00000f00;
1984 else if (rssi_level
== 2)
1985 ratr_bitmap
&= 0x00000ff0;
1987 ratr_bitmap
&= 0x00000ff5;
1989 case WIRELESS_MODE_A
:
1990 ratr_index
= RATR_INX_WIRELESS_A
;
1991 ratr_bitmap
&= 0x00000ff0;
1993 case WIRELESS_MODE_N_24G
:
1994 case WIRELESS_MODE_N_5G
:
1995 ratr_index
= RATR_INX_WIRELESS_NGB
;
1997 if (rtlphy
->rf_type
== RF_1T2R
||
1998 rtlphy
->rf_type
== RF_1T1R
) {
1999 if (curtxbw_40mhz
) {
2000 if (rssi_level
== 1)
2001 ratr_bitmap
&= 0x000f0000;
2002 else if (rssi_level
== 2)
2003 ratr_bitmap
&= 0x000ff000;
2005 ratr_bitmap
&= 0x000ff015;
2007 if (rssi_level
== 1)
2008 ratr_bitmap
&= 0x000f0000;
2009 else if (rssi_level
== 2)
2010 ratr_bitmap
&= 0x000ff000;
2012 ratr_bitmap
&= 0x000ff005;
2015 if (curtxbw_40mhz
) {
2016 if (rssi_level
== 1)
2017 ratr_bitmap
&= 0x0f0f0000;
2018 else if (rssi_level
== 2)
2019 ratr_bitmap
&= 0x0f0ff000;
2021 ratr_bitmap
&= 0x0f0ff015;
2023 if (rssi_level
== 1)
2024 ratr_bitmap
&= 0x0f0f0000;
2025 else if (rssi_level
== 2)
2026 ratr_bitmap
&= 0x0f0ff000;
2028 ratr_bitmap
&= 0x0f0ff005;
2032 if ((curtxbw_40mhz
&& curshortgi_40mhz
) ||
2033 (!curtxbw_40mhz
&& curshortgi_20mhz
)) {
2037 else if (macid
== 1)
2042 ratr_index
= RATR_INX_WIRELESS_NGB
;
2044 if (rtlphy
->rf_type
== RF_1T2R
)
2045 ratr_bitmap
&= 0x000ff0ff;
2047 ratr_bitmap
&= 0x0f0ff0ff;
2050 sta_entry
->ratr_index
= ratr_index
;
2052 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_DMESG
,
2053 "ratr_bitmap :%x\n", ratr_bitmap
);
2054 *(u32
*)&rate_mask
= (ratr_bitmap
& 0x0fffffff) |
2056 rate_mask
[4] = macid
| (shortgi
? 0x20 : 0x00) | 0x80;
2057 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_DMESG
,
2058 "Rate_index:%x, ratr_val:%x, %5phC\n",
2059 ratr_index
, ratr_bitmap
, rate_mask
);
2060 rtl92c_fill_h2c_cmd(hw
, H2C_RA_MASK
, 5, rate_mask
);
2063 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw
*hw
,
2064 struct ieee80211_sta
*sta
, u8 rssi_level
)
2066 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2068 if (rtlpriv
->dm
.useramask
)
2069 rtl92ce_update_hal_rate_mask(hw
, sta
, rssi_level
);
2071 rtl92ce_update_hal_rate_table(hw
, sta
);
2074 void rtl92ce_update_channel_access_setting(struct ieee80211_hw
*hw
)
2076 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2077 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
2080 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_SLOT_TIME
,
2082 if (!mac
->ht_enable
)
2083 sifs_timer
= 0x0a0a;
2085 sifs_timer
= 0x1010;
2086 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_SIFS
, (u8
*)&sifs_timer
);
2089 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw
*hw
, u8
*valid
)
2091 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2092 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
2093 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
2094 enum rf_pwrstate e_rfpowerstate_toset
;
2096 bool actuallyset
= false;
2099 if (rtlpci
->being_init_adapter
)
2102 if (ppsc
->swrf_processing
)
2105 spin_lock_irqsave(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2106 if (ppsc
->rfchange_inprogress
) {
2107 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2110 ppsc
->rfchange_inprogress
= true;
2111 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2114 rtl_write_byte(rtlpriv
, REG_MAC_PINMUX_CFG
, rtl_read_byte(rtlpriv
,
2115 REG_MAC_PINMUX_CFG
)&~(BIT(3)));
2117 u1tmp
= rtl_read_byte(rtlpriv
, REG_GPIO_IO_SEL
);
2118 e_rfpowerstate_toset
= (u1tmp
& BIT(3)) ? ERFON
: ERFOFF
;
2120 if ((ppsc
->hwradiooff
) && (e_rfpowerstate_toset
== ERFON
)) {
2121 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
2122 "GPIOChangeRF - HW Radio ON, RF ON\n");
2124 e_rfpowerstate_toset
= ERFON
;
2125 ppsc
->hwradiooff
= false;
2127 } else if (!ppsc
->hwradiooff
&& (e_rfpowerstate_toset
== ERFOFF
)) {
2128 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
2129 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2131 e_rfpowerstate_toset
= ERFOFF
;
2132 ppsc
->hwradiooff
= true;
2137 spin_lock_irqsave(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2138 ppsc
->rfchange_inprogress
= false;
2139 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2141 if (ppsc
->reg_rfps_level
& RT_RF_OFF_LEVL_HALT_NIC
)
2142 RT_SET_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
);
2144 spin_lock_irqsave(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2145 ppsc
->rfchange_inprogress
= false;
2146 spin_unlock_irqrestore(&rtlpriv
->locks
.rf_ps_lock
, flag
);
2150 return !ppsc
->hwradiooff
;
2154 void rtl92ce_set_key(struct ieee80211_hw
*hw
, u32 key_index
,
2155 u8
*p_macaddr
, bool is_group
, u8 enc_algo
,
2156 bool is_wepkey
, bool clear_all
)
2158 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2159 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
2160 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
2161 u8
*macaddr
= p_macaddr
;
2163 bool is_pairwise
= false;
2165 static u8 cam_const_addr
[4][6] = {
2166 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2167 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2168 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2169 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2171 static u8 cam_const_broad
[] = {
2172 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2178 u8 clear_number
= 5;
2180 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
, "clear_all\n");
2182 for (idx
= 0; idx
< clear_number
; idx
++) {
2183 rtl_cam_mark_invalid(hw
, cam_offset
+ idx
);
2184 rtl_cam_empty_entry(hw
, cam_offset
+ idx
);
2187 memset(rtlpriv
->sec
.key_buf
[idx
], 0,
2189 rtlpriv
->sec
.key_len
[idx
] = 0;
2195 case WEP40_ENCRYPTION
:
2196 enc_algo
= CAM_WEP40
;
2198 case WEP104_ENCRYPTION
:
2199 enc_algo
= CAM_WEP104
;
2201 case TKIP_ENCRYPTION
:
2202 enc_algo
= CAM_TKIP
;
2204 case AESCCMP_ENCRYPTION
:
2208 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
2209 "switch case not processed\n");
2210 enc_algo
= CAM_TKIP
;
2214 if (is_wepkey
|| rtlpriv
->sec
.use_defaultkey
) {
2215 macaddr
= cam_const_addr
[key_index
];
2216 entry_id
= key_index
;
2219 macaddr
= cam_const_broad
;
2220 entry_id
= key_index
;
2222 if (mac
->opmode
== NL80211_IFTYPE_AP
||
2223 mac
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
2224 entry_id
= rtl_cam_get_free_entry(hw
,
2226 if (entry_id
>= TOTAL_CAM_ENTRY
) {
2227 RT_TRACE(rtlpriv
, COMP_SEC
,
2229 "Can not find free hw security cam entry\n");
2233 entry_id
= CAM_PAIRWISE_KEY_POSITION
;
2236 key_index
= PAIRWISE_KEYIDX
;
2241 if (rtlpriv
->sec
.key_len
[key_index
] == 0) {
2242 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2243 "delete one entry, entry_id is %d\n",
2245 if (mac
->opmode
== NL80211_IFTYPE_AP
||
2246 mac
->opmode
== NL80211_IFTYPE_MESH_POINT
)
2247 rtl_cam_del_entry(hw
, p_macaddr
);
2248 rtl_cam_delete_one_entry(hw
, p_macaddr
, entry_id
);
2250 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_LOUD
,
2251 "The insert KEY length is %d\n",
2252 rtlpriv
->sec
.key_len
[PAIRWISE_KEYIDX
]);
2253 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_LOUD
,
2254 "The insert KEY is %x %x\n",
2255 rtlpriv
->sec
.key_buf
[0][0],
2256 rtlpriv
->sec
.key_buf
[0][1]);
2258 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2261 RT_PRINT_DATA(rtlpriv
, COMP_SEC
, DBG_LOUD
,
2262 "Pairwise Key content",
2263 rtlpriv
->sec
.pairwise_key
,
2265 key_len
[PAIRWISE_KEYIDX
]);
2267 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2268 "set Pairwise key\n");
2270 rtl_cam_add_one_entry(hw
, macaddr
, key_index
,
2272 CAM_CONFIG_NO_USEDK
,
2274 key_buf
[key_index
]);
2276 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2279 if (mac
->opmode
== NL80211_IFTYPE_ADHOC
) {
2280 rtl_cam_add_one_entry(hw
,
2283 CAM_PAIRWISE_KEY_POSITION
,
2285 CAM_CONFIG_NO_USEDK
,
2286 rtlpriv
->sec
.key_buf
2290 rtl_cam_add_one_entry(hw
, macaddr
, key_index
,
2292 CAM_CONFIG_NO_USEDK
,
2293 rtlpriv
->sec
.key_buf
[entry_id
]);
2300 static void rtl8192ce_bt_var_init(struct ieee80211_hw
*hw
)
2302 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
2304 rtlpcipriv
->bt_coexist
.bt_coexistence
=
2305 rtlpcipriv
->bt_coexist
.eeprom_bt_coexist
;
2306 rtlpcipriv
->bt_coexist
.bt_ant_num
=
2307 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_num
;
2308 rtlpcipriv
->bt_coexist
.bt_coexist_type
=
2309 rtlpcipriv
->bt_coexist
.eeprom_bt_type
;
2311 if (rtlpcipriv
->bt_coexist
.reg_bt_iso
== 2)
2312 rtlpcipriv
->bt_coexist
.bt_ant_isolation
=
2313 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_isol
;
2315 rtlpcipriv
->bt_coexist
.bt_ant_isolation
=
2316 rtlpcipriv
->bt_coexist
.reg_bt_iso
;
2318 rtlpcipriv
->bt_coexist
.bt_radio_shared_type
=
2319 rtlpcipriv
->bt_coexist
.eeprom_bt_radio_shared
;
2321 if (rtlpcipriv
->bt_coexist
.bt_coexistence
) {
2323 if (rtlpcipriv
->bt_coexist
.reg_bt_sco
== 1)
2324 rtlpcipriv
->bt_coexist
.bt_service
= BT_OTHER_ACTION
;
2325 else if (rtlpcipriv
->bt_coexist
.reg_bt_sco
== 2)
2326 rtlpcipriv
->bt_coexist
.bt_service
= BT_SCO
;
2327 else if (rtlpcipriv
->bt_coexist
.reg_bt_sco
== 4)
2328 rtlpcipriv
->bt_coexist
.bt_service
= BT_BUSY
;
2329 else if (rtlpcipriv
->bt_coexist
.reg_bt_sco
== 5)
2330 rtlpcipriv
->bt_coexist
.bt_service
= BT_OTHERBUSY
;
2332 rtlpcipriv
->bt_coexist
.bt_service
= BT_IDLE
;
2334 rtlpcipriv
->bt_coexist
.bt_edca_ul
= 0;
2335 rtlpcipriv
->bt_coexist
.bt_edca_dl
= 0;
2336 rtlpcipriv
->bt_coexist
.bt_rssi_state
= 0xff;
2340 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw
*hw
,
2341 bool auto_load_fail
, u8
*hwinfo
)
2343 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
2346 if (!auto_load_fail
) {
2347 rtlpcipriv
->bt_coexist
.eeprom_bt_coexist
=
2348 ((hwinfo
[RF_OPTION1
] & 0xe0) >> 5);
2349 val
= hwinfo
[RF_OPTION4
];
2350 rtlpcipriv
->bt_coexist
.eeprom_bt_type
= ((val
& 0xe) >> 1);
2351 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_num
= (val
& 0x1);
2352 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_isol
= ((val
& 0x10) >> 4);
2353 rtlpcipriv
->bt_coexist
.eeprom_bt_radio_shared
=
2354 ((val
& 0x20) >> 5);
2356 rtlpcipriv
->bt_coexist
.eeprom_bt_coexist
= 0;
2357 rtlpcipriv
->bt_coexist
.eeprom_bt_type
= BT_2WIRE
;
2358 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_num
= ANT_X2
;
2359 rtlpcipriv
->bt_coexist
.eeprom_bt_ant_isol
= 0;
2360 rtlpcipriv
->bt_coexist
.eeprom_bt_radio_shared
= BT_RADIO_SHARED
;
2363 rtl8192ce_bt_var_init(hw
);
2366 void rtl8192ce_bt_reg_init(struct ieee80211_hw
*hw
)
2368 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
2370 /* 0:Low, 1:High, 2:From Efuse. */
2371 rtlpcipriv
->bt_coexist
.reg_bt_iso
= 2;
2372 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2373 rtlpcipriv
->bt_coexist
.reg_bt_sco
= 3;
2374 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2375 rtlpcipriv
->bt_coexist
.reg_bt_sco
= 0;
2379 void rtl8192ce_bt_hw_init(struct ieee80211_hw
*hw
)
2381 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2382 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
2383 struct rtl_pci_priv
*rtlpcipriv
= rtl_pcipriv(hw
);
2387 if (rtlpcipriv
->bt_coexist
.bt_coexistence
&&
2388 ((rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC4
) ||
2389 rtlpcipriv
->bt_coexist
.bt_coexist_type
== BT_CSR_BC8
)) {
2391 if (rtlpcipriv
->bt_coexist
.bt_ant_isolation
)
2392 rtl_write_byte(rtlpriv
, REG_GPIO_MUXCFG
, 0xa0);
2394 u1_tmp
= rtl_read_byte(rtlpriv
, 0x4fd) &
2395 BIT_OFFSET_LEN_MASK_32(0, 1);
2397 ((rtlpcipriv
->bt_coexist
.bt_ant_isolation
== 1) ?
2398 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2399 ((rtlpcipriv
->bt_coexist
.bt_service
== BT_SCO
) ?
2400 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2401 rtl_write_byte(rtlpriv
, 0x4fd, u1_tmp
);
2403 rtl_write_dword(rtlpriv
, REG_BT_COEX_TABLE
+4, 0xaaaa9aaa);
2404 rtl_write_dword(rtlpriv
, REG_BT_COEX_TABLE
+8, 0xffbd0040);
2405 rtl_write_dword(rtlpriv
, REG_BT_COEX_TABLE
+0xc, 0x40000010);
2407 /* Config to 1T1R. */
2408 if (rtlphy
->rf_type
== RF_1T1R
) {
2409 u1_tmp
= rtl_read_byte(rtlpriv
, ROFDM0_TRXPATHENABLE
);
2410 u1_tmp
&= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2411 rtl_write_byte(rtlpriv
, ROFDM0_TRXPATHENABLE
, u1_tmp
);
2413 u1_tmp
= rtl_read_byte(rtlpriv
, ROFDM1_TRXPATHENABLE
);
2414 u1_tmp
&= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2415 rtl_write_byte(rtlpriv
, ROFDM1_TRXPATHENABLE
, u1_tmp
);
2420 void rtl92ce_suspend(struct ieee80211_hw
*hw
)
2424 void rtl92ce_resume(struct ieee80211_hw
*hw
)