drivers/net/wireless/rtlwifi/rtl8192cu/phy.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../pci.h"
  32 #include "../ps.h"
  33 #include "../core.h"
  34 #include "reg.h"
  35 #include "def.h"
  36 #include "phy.h"
  37 #include "../rtl8192c/phy_common.h"
  38 #include "rf.h"
  39 #include "dm.h"
  40 #include "../rtl8192c/dm_common.h"
  41 #include "../rtl8192c/fw_common.h"
  42 #include "table.h"
  43
  44 u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
  45                              enum radio_path rfpath, u32 regaddr, u32 bitmask)
  46 {
  47         struct rtl_priv *rtlpriv = rtl_priv(hw);
  48         u32 original_value, readback_value, bitshift;
  49         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  50
  51         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  52                  "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
  53                  regaddr, rfpath, bitmask);
  54         if (rtlphy->rf_mode != RF_OP_BY_FW) {
  55                 original_value = _rtl92c_phy_rf_serial_read(hw,
  56                                                             rfpath, regaddr);
  57         } else {
  58                 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
  59                                                                rfpath, regaddr);
  60         }
  61         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  62         readback_value = (original_value & bitmask) >> bitshift;
  63         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  64                  "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
  65                  regaddr, rfpath, bitmask, original_value);
  66         return readback_value;
  67 }
  68
  69 void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw,
  70                             enum radio_path rfpath,
  71                             u32 regaddr, u32 bitmask, u32 data)
  72 {
  73         struct rtl_priv *rtlpriv = rtl_priv(hw);
  74         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  75         u32 original_value, bitshift;
  76
  77         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  78                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
  79                  regaddr, bitmask, data, rfpath);
  80         if (rtlphy->rf_mode != RF_OP_BY_FW) {
  81                 if (bitmask != RFREG_OFFSET_MASK) {
  82                         original_value = _rtl92c_phy_rf_serial_read(hw,
  83                                                                     rfpath,
  84                                                                     regaddr);
  85                         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  86                         data =
  87                             ((original_value & (~bitmask)) |
  88                              (data << bitshift));
  89                 }
  90                 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
  91         } else {
  92                 if (bitmask != RFREG_OFFSET_MASK) {
  93                         original_value = _rtl92c_phy_fw_rf_serial_read(hw,
  94                                                                        rfpath,
  95                                                                        regaddr);
  96                         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  97                         data =
  98                             ((original_value & (~bitmask)) |
  99                              (data << bitshift));
 100                 }
 101                 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
 102         }
 103         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 104                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 105                  regaddr, bitmask, data, rfpath);
 106 }
 107
 108 bool rtl92cu_phy_mac_config(struct ieee80211_hw *hw)
 109 {
 110         bool rtstatus;
 111         struct rtl_priv *rtlpriv = rtl_priv(hw);
 112         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 113         bool is92c = IS_92C_SERIAL(rtlhal->version);
 114
 115         rtstatus = _rtl92cu_phy_config_mac_with_headerfile(hw);
 116         if (is92c && IS_HARDWARE_TYPE_8192CE(rtlhal))
 117                 rtl_write_byte(rtlpriv, 0x14, 0x71);
 118         return rtstatus;
 119 }
 120
 121 bool rtl92cu_phy_bb_config(struct ieee80211_hw *hw)
 122 {
 123         bool rtstatus = true;
 124         struct rtl_priv *rtlpriv = rtl_priv(hw);
 125         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 126         u16 regval;
 127         u32 regval32;
 128         u8 b_reg_hwparafile = 1;
 129
 130         _rtl92c_phy_init_bb_rf_register_definition(hw);
 131         regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 132         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) |
 133                        BIT(0) | BIT(1));
 134         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
 135         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
 136         rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
 137         if (IS_HARDWARE_TYPE_8192CE(rtlhal)) {
 138                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
 139                                FEN_DIO_PCIE |   FEN_BB_GLB_RSTn | FEN_BBRSTB);
 140         } else if (IS_HARDWARE_TYPE_8192CU(rtlhal)) {
 141                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD |
 142                                FEN_BB_GLB_RSTn | FEN_BBRSTB);
 143         }
 144         regval32 = rtl_read_dword(rtlpriv, 0x87c);
 145         rtl_write_dword(rtlpriv, 0x87c, regval32 & (~BIT(31)));
 146         if (IS_HARDWARE_TYPE_8192CU(rtlhal))
 147                 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
 148         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
 149         if (b_reg_hwparafile == 1)
 150                 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
 151         return rtstatus;
 152 }
 153
 154 bool _rtl92cu_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
 155 {
 156         struct rtl_priv *rtlpriv = rtl_priv(hw);
 157         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 158         u32 i;
 159         u32 arraylength;
 160         u32 *ptrarray;
 161
 162         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
 163         arraylength =  rtlphy->hwparam_tables[MAC_REG].length ;
 164         ptrarray = rtlphy->hwparam_tables[MAC_REG].pdata;
 165         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CEMAC_2T_ARRAY\n");
 166         for (i = 0; i < arraylength; i = i + 2)
 167                 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
 168         return true;
 169 }
 170
 171 bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
 172                                             u8 configtype)
 173 {
 174         int i;
 175         u32 *phy_regarray_table;
 176         u32 *agctab_array_table;
 177         u16 phy_reg_arraylen, agctab_arraylen;
 178         struct rtl_priv *rtlpriv = rtl_priv(hw);
 179         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 180         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 181
 182         if (IS_92C_SERIAL(rtlhal->version)) {
 183                 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_2T].length;
 184                 agctab_array_table =  rtlphy->hwparam_tables[AGCTAB_2T].pdata;
 185                 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_2T].length;
 186                 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_2T].pdata;
 187         } else {
 188                 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_1T].length;
 189                 agctab_array_table =  rtlphy->hwparam_tables[AGCTAB_1T].pdata;
 190                 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_1T].length;
 191                 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_1T].pdata;
 192         }
 193         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 194                 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
 195                         rtl_addr_delay(phy_regarray_table[i]);
 196                         rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
 197                                       phy_regarray_table[i + 1]);
 198                         udelay(1);
 199                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 200                                  "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
 201                                  phy_regarray_table[i],
 202                                  phy_regarray_table[i + 1]);
 203                 }
 204         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 205                 for (i = 0; i < agctab_arraylen; i = i + 2) {
 206                         rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
 207                                       agctab_array_table[i + 1]);
 208                         udelay(1);
 209                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 210                                  "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
 211                                  agctab_array_table[i],
 212                                  agctab_array_table[i + 1]);
 213                 }
 214         }
 215         return true;
 216 }
 217
 218 bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
 219                                               u8 configtype)
 220 {
 221         struct rtl_priv *rtlpriv = rtl_priv(hw);
 222         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 223         int i;
 224         u32 *phy_regarray_table_pg;
 225         u16 phy_regarray_pg_len;
 226
 227         rtlphy->pwrgroup_cnt = 0;
 228         phy_regarray_pg_len = rtlphy->hwparam_tables[PHY_REG_PG].length;
 229         phy_regarray_table_pg = rtlphy->hwparam_tables[PHY_REG_PG].pdata;
 230         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 231                 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
 232                         rtl_addr_delay(phy_regarray_table_pg[i]);
 233                         _rtl92c_store_pwrIndex_diffrate_offset(hw,
 234                                                   phy_regarray_table_pg[i],
 235                                                   phy_regarray_table_pg[i + 1],
 236                                                   phy_regarray_table_pg[i + 2]);
 237                 }
 238         } else {
 239                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 240                          "configtype != BaseBand_Config_PHY_REG\n");
 241         }
 242         return true;
 243 }
 244
 245 bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 246                                           enum radio_path rfpath)
 247 {
 248         int i;
 249         u32 *radioa_array_table;
 250         u32 *radiob_array_table;
 251         u16 radioa_arraylen, radiob_arraylen;
 252         struct rtl_priv *rtlpriv = rtl_priv(hw);
 253         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 254         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 255
 256         if (IS_92C_SERIAL(rtlhal->version)) {
 257                 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_2T].length;
 258                 radioa_array_table = rtlphy->hwparam_tables[RADIOA_2T].pdata;
 259                 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_2T].length;
 260                 radiob_array_table = rtlphy->hwparam_tables[RADIOB_2T].pdata;
 261                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 262                          "Radio_A:RTL8192CERADIOA_2TARRAY\n");
 263                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 264                          "Radio_B:RTL8192CE_RADIOB_2TARRAY\n");
 265         } else {
 266                 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_1T].length;
 267                 radioa_array_table = rtlphy->hwparam_tables[RADIOA_1T].pdata;
 268                 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_1T].length;
 269                 radiob_array_table = rtlphy->hwparam_tables[RADIOB_1T].pdata;
 270                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 271                          "Radio_A:RTL8192CE_RADIOA_1TARRAY\n");
 272                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 273                          "Radio_B:RTL8192CE_RADIOB_1TARRAY\n");
 274         }
 275         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
 276         switch (rfpath) {
 277         case RF90_PATH_A:
 278                 for (i = 0; i < radioa_arraylen; i = i + 2) {
 279                         rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
 280                                         RFREG_OFFSET_MASK,
 281                                         radioa_array_table[i + 1]);
 282                 }
 283                 break;
 284         case RF90_PATH_B:
 285                 for (i = 0; i < radiob_arraylen; i = i + 2) {
 286                         rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
 287                                         RFREG_OFFSET_MASK,
 288                                         radiob_array_table[i + 1]);
 289                 }
 290                 break;
 291         case RF90_PATH_C:
 292                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 293                          "switch case not processed\n");
 294                 break;
 295         case RF90_PATH_D:
 296                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 297                          "switch case not processed\n");
 298                 break;
 299         default:
 300                 break;
 301         }
 302         return true;
 303 }
 304
 305 void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
 306 {
 307         struct rtl_priv *rtlpriv = rtl_priv(hw);
 308         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 309         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 310         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 311         u8 reg_bw_opmode;
 312         u8 reg_prsr_rsc;
 313
 314         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
 315                  rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 316                  "20MHz" : "40MHz");
 317         if (is_hal_stop(rtlhal)) {
 318                 rtlphy->set_bwmode_inprogress = false;
 319                 return;
 320         }
 321         reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
 322         reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
 323         switch (rtlphy->current_chan_bw) {
 324         case HT_CHANNEL_WIDTH_20:
 325                 reg_bw_opmode |= BW_OPMODE_20MHZ;
 326                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 327                 break;
 328         case HT_CHANNEL_WIDTH_20_40:
 329                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 330                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 331                 reg_prsr_rsc =
 332                     (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
 333                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
 334                 break;
 335         default:
 336                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 337                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 338                 break;
 339         }
 340         switch (rtlphy->current_chan_bw) {
 341         case HT_CHANNEL_WIDTH_20:
 342                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
 343                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
 344                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 345                 break;
 346         case HT_CHANNEL_WIDTH_20_40:
 347                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
 348                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
 349                 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
 350                               (mac->cur_40_prime_sc >> 1));
 351                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
 352                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
 353                 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
 354                               (mac->cur_40_prime_sc ==
 355                                HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
 356                 break;
 357         default:
 358                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 359                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 360                 break;
 361         }
 362         rtl92cu_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
 363         rtlphy->set_bwmode_inprogress = false;
 364         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
 365 }
 366
 367 void rtl92cu_bb_block_on(struct ieee80211_hw *hw)
 368 {
 369         struct rtl_priv *rtlpriv = rtl_priv(hw);
 370
 371         mutex_lock(&rtlpriv->io.bb_mutex);
 372         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 373         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 374         mutex_unlock(&rtlpriv->io.bb_mutex);
 375 }
 376
 377 void _rtl92cu_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
 378 {
 379         u8 tmpreg;
 380         u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
 381         struct rtl_priv *rtlpriv = rtl_priv(hw);
 382
 383         tmpreg = rtl_read_byte(rtlpriv, 0xd03);
 384
 385         if ((tmpreg & 0x70) != 0)
 386                 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
 387         else
 388                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
 389
 390         if ((tmpreg & 0x70) != 0) {
 391                 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
 392                 if (is2t)
 393                         rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
 394                                                   MASK12BITS);
 395                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
 396                               (rf_a_mode & 0x8FFFF) | 0x10000);
 397                 if (is2t)
 398                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 399                                       (rf_b_mode & 0x8FFFF) | 0x10000);
 400         }
 401         lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
 402         rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
 403         mdelay(100);
 404         if ((tmpreg & 0x70) != 0) {
 405                 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
 406                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
 407                 if (is2t)
 408                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 409                                       rf_b_mode);
 410         } else {
 411                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
 412         }
 413 }
 414
 415 static bool _rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
 416                                             enum rf_pwrstate rfpwr_state)
 417 {
 418         struct rtl_priv *rtlpriv = rtl_priv(hw);
 419         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 420         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 421         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 422         bool bresult = true;
 423         u8 i, queue_id;
 424         struct rtl8192_tx_ring *ring = NULL;
 425
 426         switch (rfpwr_state) {
 427         case ERFON:
 428                 if ((ppsc->rfpwr_state == ERFOFF) &&
 429                     RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
 430                         bool rtstatus;
 431                         u32 InitializeCount = 0;
 432
 433                         do {
 434                                 InitializeCount++;
 435                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 436                                          "IPS Set eRf nic enable\n");
 437                                 rtstatus = rtl_ps_enable_nic(hw);
 438                         } while (!rtstatus && (InitializeCount < 10));
 439                         RT_CLEAR_PS_LEVEL(ppsc,
 440                                           RT_RF_OFF_LEVL_HALT_NIC);
 441                 } else {
 442                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 443                                  "Set ERFON sleeped:%d ms\n",
 444                                  jiffies_to_msecs(jiffies -
 445                                                   ppsc->last_sleep_jiffies));
 446                         ppsc->last_awake_jiffies = jiffies;
 447                         rtl92ce_phy_set_rf_on(hw);
 448                 }
 449                 if (mac->link_state == MAC80211_LINKED) {
 450                         rtlpriv->cfg->ops->led_control(hw,
 451                                                        LED_CTL_LINK);
 452                 } else {
 453                         rtlpriv->cfg->ops->led_control(hw,
 454                                                        LED_CTL_NO_LINK);
 455                 }
 456                 break;
 457         case ERFOFF:
 458                 for (queue_id = 0, i = 0;
 459                      queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 460                         ring = &pcipriv->dev.tx_ring[queue_id];
 461                         if (skb_queue_len(&ring->queue) == 0 ||
 462                                 queue_id == BEACON_QUEUE) {
 463                                 queue_id++;
 464                                 continue;
 465                         } else {
 466                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 467                                          "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
 468                                          i + 1,
 469                                          queue_id,
 470                                          skb_queue_len(&ring->queue));
 471                                 udelay(10);
 472                                 i++;
 473                         }
 474                         if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 475                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 476                                          "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
 477                                          MAX_DOZE_WAITING_TIMES_9x,
 478                                          queue_id,
 479                                          skb_queue_len(&ring->queue));
 480                                 break;
 481                         }
 482                 }
 483                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
 484                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 485                                  "IPS Set eRf nic disable\n");
 486                         rtl_ps_disable_nic(hw);
 487                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 488                 } else {
 489                         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
 490                                 rtlpriv->cfg->ops->led_control(hw,
 491                                                          LED_CTL_NO_LINK);
 492                         } else {
 493                                 rtlpriv->cfg->ops->led_control(hw,
 494                                                          LED_CTL_POWER_OFF);
 495                         }
 496                 }
 497                 break;
 498         case ERFSLEEP:
 499                 if (ppsc->rfpwr_state == ERFOFF)
 500                         return false;
 501                 for (queue_id = 0, i = 0;
 502                      queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 503                         ring = &pcipriv->dev.tx_ring[queue_id];
 504                         if (skb_queue_len(&ring->queue) == 0) {
 505                                 queue_id++;
 506                                 continue;
 507                         } else {
 508                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 509                                          "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
 510                                          i + 1, queue_id,
 511                                          skb_queue_len(&ring->queue));
 512                                 udelay(10);
 513                                 i++;
 514                         }
 515                         if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 516                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 517                                          "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
 518                                          MAX_DOZE_WAITING_TIMES_9x,
 519                                          queue_id,
 520                                          skb_queue_len(&ring->queue));
 521                                 break;
 522                         }
 523                 }
 524                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 525                          "Set ERFSLEEP awaked:%d ms\n",
 526                          jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
 527                 ppsc->last_sleep_jiffies = jiffies;
 528                 _rtl92c_phy_set_rf_sleep(hw);
 529                 break;
 530         default:
 531                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 532                          "switch case not processed\n");
 533                 bresult = false;
 534                 break;
 535         }
 536         if (bresult)
 537                 ppsc->rfpwr_state = rfpwr_state;
 538         return bresult;
 539 }
 540
 541 bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
 542                                     enum rf_pwrstate rfpwr_state)
 543 {
 544         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 545         bool bresult = false;
 546
 547         if (rfpwr_state == ppsc->rfpwr_state)
 548                 return bresult;
 549         bresult = _rtl92cu_phy_set_rf_power_state(hw, rfpwr_state);
 550         return bresult;
 551 }