powerpc/eeh: Fix PE#0 check in eeh_add_to_parent_pe()
[linux/fpc-iii.git] / drivers / net / wireless / rtlwifi / rtl8192cu / table.h
blob4b020e9e30b1eb8a2f559b41c5906e10276c5e9a
1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
30 #ifndef __RTL92CU_TABLE__H_
31 #define __RTL92CU_TABLE__H_
33 #include <linux/types.h>
35 #define RTL8192CUPHY_REG_2TARRAY_LENGTH 374
36 extern u32 RTL8192CUPHY_REG_2TARRAY[RTL8192CUPHY_REG_2TARRAY_LENGTH];
37 #define RTL8192CUPHY_REG_1TARRAY_LENGTH 374
38 extern u32 RTL8192CUPHY_REG_1TARRAY[RTL8192CUPHY_REG_1TARRAY_LENGTH];
40 #define RTL8192CUPHY_REG_ARRAY_PGLENGTH 336
41 extern u32 RTL8192CUPHY_REG_ARRAY_PG[RTL8192CUPHY_REG_ARRAY_PGLENGTH];
43 #define RTL8192CURADIOA_2TARRAYLENGTH 282
44 extern u32 RTL8192CURADIOA_2TARRAY[RTL8192CURADIOA_2TARRAYLENGTH];
45 #define RTL8192CURADIOB_2TARRAYLENGTH 78
46 extern u32 RTL8192CU_RADIOB_2TARRAY[RTL8192CURADIOB_2TARRAYLENGTH];
47 #define RTL8192CURADIOA_1TARRAYLENGTH 282
48 extern u32 RTL8192CU_RADIOA_1TARRAY[RTL8192CURADIOA_1TARRAYLENGTH];
49 #define RTL8192CURADIOB_1TARRAYLENGTH 1
50 extern u32 RTL8192CU_RADIOB_1TARRAY[RTL8192CURADIOB_1TARRAYLENGTH];
52 #define RTL8192CUMAC_2T_ARRAYLENGTH 172
53 extern u32 RTL8192CUMAC_2T_ARRAY[RTL8192CUMAC_2T_ARRAYLENGTH];
55 #define RTL8192CUAGCTAB_2TARRAYLENGTH 320
56 extern u32 RTL8192CUAGCTAB_2TARRAY[RTL8192CUAGCTAB_2TARRAYLENGTH];
57 #define RTL8192CUAGCTAB_1TARRAYLENGTH 320
58 extern u32 RTL8192CUAGCTAB_1TARRAY[RTL8192CUAGCTAB_1TARRAYLENGTH];
60 #define RTL8192CUPHY_REG_1T_HPArrayLength 378
61 extern u32 RTL8192CUPHY_REG_1T_HPArray[RTL8192CUPHY_REG_1T_HPArrayLength];
63 #define RTL8192CUPHY_REG_Array_PG_HPLength 336
64 extern u32 RTL8192CUPHY_REG_Array_PG_HP[RTL8192CUPHY_REG_Array_PG_HPLength];
66 #define RTL8192CURadioA_1T_HPArrayLength 282
67 extern u32 RTL8192CURadioA_1T_HPArray[RTL8192CURadioA_1T_HPArrayLength];
68 #define RTL8192CUAGCTAB_1T_HPArrayLength 320
69 extern u32 Rtl8192CUAGCTAB_1T_HPArray[RTL8192CUAGCTAB_1T_HPArrayLength];
71 #endif