drivers/net/wireless/rtlwifi/rtl8192ee/sw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../core.h"
  28 #include "../pci.h"
  29 #include "reg.h"
  30 #include "def.h"
  31 #include "phy.h"
  32 #include "dm.h"
  33 #include "hw.h"
  34 #include "sw.h"
  35 #include "fw.h"
  36 #include "trx.h"
  37 #include "led.h"
  38 #include "table.h"
  39
  40 #include "../btcoexist/rtl_btc.h"
  41
  42 #include <linux/vmalloc.h>
  43 #include <linux/module.h>
  44
  45 static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw)
  46 {
  47         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  48
  49         /*close ASPM for AMD defaultly */
  50         rtlpci->const_amdpci_aspm = 0;
  51
  52         /**
  53          * ASPM PS mode.
  54          * 0 - Disable ASPM,
  55          * 1 - Enable ASPM without Clock Req,
  56          * 2 - Enable ASPM with Clock Req,
  57          * 3 - Alwyas Enable ASPM with Clock Req,
  58          * 4 - Always Enable ASPM without Clock Req.
  59          * set defult to RTL8192CE:3 RTL8192E:2
  60          */
  61         rtlpci->const_pci_aspm = 3;
  62
  63         /*Setting for PCI-E device */
  64         rtlpci->const_devicepci_aspm_setting = 0x03;
  65
  66         /*Setting for PCI-E bridge */
  67         rtlpci->const_hostpci_aspm_setting = 0x02;
  68
  69         /**
  70          * In Hw/Sw Radio Off situation.
  71          * 0 - Default,
  72          * 1 - From ASPM setting without low Mac Pwr,
  73          * 2 - From ASPM setting with low Mac Pwr,
  74          * 3 - Bus D3
  75          * set default to RTL8192CE:0 RTL8192SE:2
  76          */
  77         rtlpci->const_hwsw_rfoff_d3 = 0;
  78
  79         /**
  80          * This setting works for those device with
  81          * backdoor ASPM setting such as EPHY setting.
  82          * 0 - Not support ASPM,
  83          * 1 - Support ASPM,
  84          * 2 - According to chipset.
  85          */
  86         rtlpci->const_support_pciaspm = 1;
  87 }
  88
  89 int rtl92ee_init_sw_vars(struct ieee80211_hw *hw)
  90 {
  91         struct rtl_priv *rtlpriv = rtl_priv(hw);
  92         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  93         int err = 0;
  94
  95         rtl92ee_bt_reg_init(hw);
  96         rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
  97         rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
  98
  99         rtlpriv->dm.dm_initialgain_enable = 1;
 100         rtlpriv->dm.dm_flag = 0;
 101         rtlpriv->dm.disable_framebursting = 0;
 102         rtlpci->transmit_config = CFENDFORM | BIT(15);
 103
 104         /*just 2.4G band*/
 105         rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
 106         rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
 107         rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
 108
 109         rtlpci->receive_config = (RCR_APPFCS                    |
 110                                   RCR_APP_MIC                   |
 111                                   RCR_APP_ICV                   |
 112                                   RCR_APP_PHYST_RXFF            |
 113                                   RCR_HTC_LOC_CTRL              |
 114                                   RCR_AMF                       |
 115                                   RCR_ACF                       |
 116                                   RCR_ACRC32                    |
 117                                   RCR_AB                        |
 118                                   RCR_AM                        |
 119                                   RCR_APM                       |
 120                                   0);
 121
 122         rtlpci->irq_mask[0] = (u32)(IMR_PSTIMEOUT               |
 123                                      IMR_C2HCMD                 |
 124                                      IMR_HIGHDOK                |
 125                                      IMR_MGNTDOK                |
 126                                      IMR_BKDOK                  |
 127                                      IMR_BEDOK                  |
 128                                      IMR_VIDOK                  |
 129                                      IMR_VODOK                  |
 130                                      IMR_RDU                    |
 131                                      IMR_ROK                    |
 132                                      0);
 133         rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);
 134
 135         /* for debug level */
 136         rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
 137         /* for LPS & IPS */
 138         rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
 139         rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
 140         rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
 141         rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
 142         if (rtlpriv->cfg->mod_params->disable_watchdog)
 143                 pr_info("watchdog disabled\n");
 144         rtlpriv->psc.reg_fwctrl_lps = 3;
 145         rtlpriv->psc.reg_max_lps_awakeintvl = 5;
 146         /* for ASPM, you can close aspm through
 147          * set const_support_pciaspm = 0
 148          */
 149         rtl92ee_init_aspm_vars(hw);
 150
 151         if (rtlpriv->psc.reg_fwctrl_lps == 1)
 152                 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 153         else if (rtlpriv->psc.reg_fwctrl_lps == 2)
 154                 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 155         else if (rtlpriv->psc.reg_fwctrl_lps == 3)
 156                 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 157
 158         /* for early mode */
 159         rtlpriv->rtlhal.earlymode_enable = false;
 160
 161         /*low power */
 162         rtlpriv->psc.low_power_enable = false;
 163
 164         /* for firmware buf */
 165         rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
 166         if (!rtlpriv->rtlhal.pfirmware) {
 167                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 168                          "Can't alloc buffer for fw\n");
 169                 return 1;
 170         }
 171
 172         /* request fw */
 173         rtlpriv->cfg->fw_name = "rtlwifi/rtl8192eefw.bin";
 174
 175         rtlpriv->max_fw_size = 0x8000;
 176         pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
 177         err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
 178                                       rtlpriv->io.dev, GFP_KERNEL, hw,
 179                                       rtl_fw_cb);
 180         if (err) {
 181                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 182                          "Failed to request firmware!\n");
 183                 return 1;
 184         }
 185
 186         return 0;
 187 }
 188
 189 void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw)
 190 {
 191         struct rtl_priv *rtlpriv = rtl_priv(hw);
 192
 193         if (rtlpriv->rtlhal.pfirmware) {
 194                 vfree(rtlpriv->rtlhal.pfirmware);
 195                 rtlpriv->rtlhal.pfirmware = NULL;
 196         }
 197 }
 198
 199 /* get bt coexist status */
 200 bool rtl92ee_get_btc_status(void)
 201 {
 202         return true;
 203 }
 204
 205 static struct rtl_hal_ops rtl8192ee_hal_ops = {
 206         .init_sw_vars = rtl92ee_init_sw_vars,
 207         .deinit_sw_vars = rtl92ee_deinit_sw_vars,
 208         .read_eeprom_info = rtl92ee_read_eeprom_info,
 209         .interrupt_recognized = rtl92ee_interrupt_recognized,/*need check*/
 210         .hw_init = rtl92ee_hw_init,
 211         .hw_disable = rtl92ee_card_disable,
 212         .hw_suspend = rtl92ee_suspend,
 213         .hw_resume = rtl92ee_resume,
 214         .enable_interrupt = rtl92ee_enable_interrupt,
 215         .disable_interrupt = rtl92ee_disable_interrupt,
 216         .set_network_type = rtl92ee_set_network_type,
 217         .set_chk_bssid = rtl92ee_set_check_bssid,
 218         .set_qos = rtl92ee_set_qos,
 219         .set_bcn_reg = rtl92ee_set_beacon_related_registers,
 220         .set_bcn_intv = rtl92ee_set_beacon_interval,
 221         .update_interrupt_mask = rtl92ee_update_interrupt_mask,
 222         .get_hw_reg = rtl92ee_get_hw_reg,
 223         .set_hw_reg = rtl92ee_set_hw_reg,
 224         .update_rate_tbl = rtl92ee_update_hal_rate_tbl,
 225         .pre_fill_tx_bd_desc = rtl92ee_pre_fill_tx_bd_desc,
 226         .rx_desc_buff_remained_cnt = rtl92ee_rx_desc_buff_remained_cnt,
 227         .rx_check_dma_ok = rtl92ee_rx_check_dma_ok,
 228         .fill_tx_desc = rtl92ee_tx_fill_desc,
 229         .fill_tx_cmddesc = rtl92ee_tx_fill_cmddesc,
 230         .query_rx_desc = rtl92ee_rx_query_desc,
 231         .set_channel_access = rtl92ee_update_channel_access_setting,
 232         .radio_onoff_checking = rtl92ee_gpio_radio_on_off_checking,
 233         .set_bw_mode = rtl92ee_phy_set_bw_mode,
 234         .switch_channel = rtl92ee_phy_sw_chnl,
 235         .dm_watchdog = rtl92ee_dm_watchdog,
 236         .scan_operation_backup = rtl92ee_phy_scan_operation_backup,
 237         .set_rf_power_state = rtl92ee_phy_set_rf_power_state,
 238         .led_control = rtl92ee_led_control,
 239         .set_desc = rtl92ee_set_desc,
 240         .get_desc = rtl92ee_get_desc,
 241         .is_tx_desc_closed = rtl92ee_is_tx_desc_closed,
 242         .get_available_desc = rtl92ee_get_available_desc,
 243         .tx_polling = rtl92ee_tx_polling,
 244         .enable_hw_sec = rtl92ee_enable_hw_security_config,
 245         .set_key = rtl92ee_set_key,
 246         .init_sw_leds = rtl92ee_init_sw_leds,
 247         .get_bbreg = rtl92ee_phy_query_bb_reg,
 248         .set_bbreg = rtl92ee_phy_set_bb_reg,
 249         .get_rfreg = rtl92ee_phy_query_rf_reg,
 250         .set_rfreg = rtl92ee_phy_set_rf_reg,
 251         .fill_h2c_cmd = rtl92ee_fill_h2c_cmd,
 252         .get_btc_status = rtl92ee_get_btc_status,
 253         .rx_command_packet = rtl92ee_rx_command_packet,
 254 };
 255
 256 static struct rtl_mod_params rtl92ee_mod_params = {
 257         .sw_crypto = false,
 258         .inactiveps = false,
 259         .swctrl_lps = false,
 260         .fwctrl_lps = true,
 261         .msi_support = true,
 262         .debug = DBG_EMERG,
 263 };
 264
 265 static struct rtl_hal_cfg rtl92ee_hal_cfg = {
 266         .bar_id = 2,
 267         .write_readback = true,
 268         .name = "rtl92ee_pci",
 269         .fw_name = "rtlwifi/rtl8192eefw.bin",
 270         .ops = &rtl8192ee_hal_ops,
 271         .mod_params = &rtl92ee_mod_params,
 272
 273         .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
 274         .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
 275         .maps[SYS_CLK] = REG_SYS_CLKR,
 276         .maps[MAC_RCR_AM] = AM,
 277         .maps[MAC_RCR_AB] = AB,
 278         .maps[MAC_RCR_ACRC32] = ACRC32,
 279         .maps[MAC_RCR_ACF] = ACF,
 280         .maps[MAC_RCR_AAP] = AAP,
 281         .maps[MAC_HIMR] = REG_HIMR,
 282         .maps[MAC_HIMRE] = REG_HIMRE,
 283
 284         .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
 285
 286         .maps[EFUSE_TEST] = REG_EFUSE_TEST,
 287         .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
 288         .maps[EFUSE_CLK] = 0,
 289         .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
 290         .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
 291         .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
 292         .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
 293         .maps[EFUSE_ANA8M] = ANA8M,
 294         .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
 295         .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 296         .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 297         .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
 298
 299         .maps[RWCAM] = REG_CAMCMD,
 300         .maps[WCAMI] = REG_CAMWRITE,
 301         .maps[RCAMO] = REG_CAMREAD,
 302         .maps[CAMDBG] = REG_CAMDBG,
 303         .maps[SECR] = REG_SECCFG,
 304         .maps[SEC_CAM_NONE] = CAM_NONE,
 305         .maps[SEC_CAM_WEP40] = CAM_WEP40,
 306         .maps[SEC_CAM_TKIP] = CAM_TKIP,
 307         .maps[SEC_CAM_AES] = CAM_AES,
 308         .maps[SEC_CAM_WEP104] = CAM_WEP104,
 309
 310         .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 311         .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 312         .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 313         .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 314         .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 315         .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 316         .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 317         .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 318         .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 319         .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 320         .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 321         .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 322         .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 323
 324         .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
 325         .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
 326         .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
 327         .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
 328         .maps[RTL_IMR_RDU] = IMR_RDU,
 329         .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
 330         .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
 331         .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
 332         .maps[RTL_IMR_TBDER] = IMR_TBDER,
 333         .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
 334         .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
 335         .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
 336         .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
 337         .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
 338         .maps[RTL_IMR_VODOK] = IMR_VODOK,
 339         .maps[RTL_IMR_ROK] = IMR_ROK,
 340         .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
 341
 342         .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
 343         .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
 344         .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
 345         .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
 346         .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
 347         .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
 348         .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
 349         .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
 350         .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
 351         .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
 352         .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
 353         .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
 354
 355         .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
 356         .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
 357 };
 358
 359 static struct pci_device_id rtl92ee_pci_ids[] = {
 360         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x818B, rtl92ee_hal_cfg)},
 361         {},
 362 };
 363
 364 MODULE_DEVICE_TABLE(pci, rtl92ee_pci_ids);
 365
 366 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 367 MODULE_AUTHOR("Larry Finger     <Larry.Finger@lwfinger.net>");
 368 MODULE_LICENSE("GPL");
 369 MODULE_DESCRIPTION("Realtek 8192EE 802.11n PCI wireless");
 370 MODULE_FIRMWARE("rtlwifi/rtl8192eefw.bin");
 371
 372 module_param_named(swenc, rtl92ee_mod_params.sw_crypto, bool, 0444);
 373 module_param_named(debug, rtl92ee_mod_params.debug, int, 0444);
 374 module_param_named(ips, rtl92ee_mod_params.inactiveps, bool, 0444);
 375 module_param_named(swlps, rtl92ee_mod_params.swctrl_lps, bool, 0444);
 376 module_param_named(fwlps, rtl92ee_mod_params.fwctrl_lps, bool, 0444);
 377 module_param_named(msi, rtl92ee_mod_params.msi_support, bool, 0444);
 378 module_param_named(disable_watchdog, rtl92ee_mod_params.disable_watchdog,
 379                    bool, 0444);
 380 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
 381 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
 382 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
 383 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
 384 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
 385 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
 386 MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
 387
 388 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
 389
 390 static struct pci_driver rtl92ee_driver = {
 391         .name = KBUILD_MODNAME,
 392         .id_table = rtl92ee_pci_ids,
 393         .probe = rtl_pci_probe,
 394         .remove = rtl_pci_disconnect,
 395         .driver.pm = &rtlwifi_pm_ops,
 396 };
 397
 398 module_pci_driver(rtl92ee_driver);