drivers/net/wireless/rtlwifi/rtl8192ee/trx.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __RTL92E_TRX_H__
  27 #define __RTL92E_TRX_H__
  28
  29 #if (DMA_IS_64BIT == 1)
  30 #if (RTL8192EE_SEG_NUM == 2)
  31 #define TX_BD_DESC_SIZE                                 128
  32 #elif (RTL8192EE_SEG_NUM == 1)
  33 #define TX_BD_DESC_SIZE                                 64
  34 #elif (RTL8192EE_SEG_NUM == 0)
  35 #define TX_BD_DESC_SIZE                                 32
  36 #endif
  37 #else
  38 #if (RTL8192EE_SEG_NUM == 2)
  39 #define TX_BD_DESC_SIZE                                 64
  40 #elif (RTL8192EE_SEG_NUM == 1)
  41 #define TX_BD_DESC_SIZE                                 32
  42 #elif (RTL8192EE_SEG_NUM == 0)
  43 #define TX_BD_DESC_SIZE                                 16
  44 #endif
  45 #endif
  46
  47 #define TX_DESC_SIZE                                    64
  48
  49 #define RX_DRV_INFO_SIZE_UNIT                           8
  50
  51 #define TX_DESC_NEXT_DESC_OFFSET                        40
  52 #define USB_HWDESC_HEADER_LEN                           40
  53
  54 #define RX_DESC_SIZE                                    24
  55 #define MAX_RECEIVE_BUFFER_SIZE                         8192
  56
  57 #define SET_TX_DESC_PKT_SIZE(__pdesc, __val)            \
  58         SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val)
  59 #define SET_TX_DESC_OFFSET(__pdesc, __val)              \
  60         SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val)
  61 #define SET_TX_DESC_BMC(__pdesc, __val)                 \
  62         SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val)
  63 #define SET_TX_DESC_HTC(__pdesc, __val)                 \
  64         SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val)
  65 #define SET_TX_DESC_LAST_SEG(__pdesc, __val)            \
  66         SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val)
  67 #define SET_TX_DESC_FIRST_SEG(__pdesc, __val)           \
  68         SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val)
  69 #define SET_TX_DESC_LINIP(__pdesc, __val)               \
  70         SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val)
  71 #define SET_TX_DESC_NO_ACM(__pdesc, __val)              \
  72         SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val)
  73 #define SET_TX_DESC_GF(__pdesc, __val)                  \
  74         SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
  75 #define SET_TX_DESC_OWN(__pdesc, __val)                 \
  76         SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
  77
  78 #define GET_TX_DESC_PKT_SIZE(__pdesc)                   \
  79         LE_BITS_TO_4BYTE(__pdesc, 0, 16)
  80 #define GET_TX_DESC_OFFSET(__pdesc)                     \
  81         LE_BITS_TO_4BYTE(__pdesc, 16, 8)
  82 #define GET_TX_DESC_BMC(__pdesc)                        \
  83         LE_BITS_TO_4BYTE(__pdesc, 24, 1)
  84 #define GET_TX_DESC_HTC(__pdesc)                        \
  85         LE_BITS_TO_4BYTE(__pdesc, 25, 1)
  86 #define GET_TX_DESC_LAST_SEG(__pdesc)                   \
  87         LE_BITS_TO_4BYTE(__pdesc, 26, 1)
  88 #define GET_TX_DESC_FIRST_SEG(__pdesc)                  \
  89         LE_BITS_TO_4BYTE(__pdesc, 27, 1)
  90 #define GET_TX_DESC_LINIP(__pdesc)                      \
  91         LE_BITS_TO_4BYTE(__pdesc, 28, 1)
  92 #define GET_TX_DESC_NO_ACM(__pdesc)                     \
  93         LE_BITS_TO_4BYTE(__pdesc, 29, 1)
  94 #define GET_TX_DESC_GF(__pdesc)                         \
  95         LE_BITS_TO_4BYTE(__pdesc, 30, 1)
  96 #define GET_TX_DESC_OWN(__pdesc)                        \
  97         LE_BITS_TO_4BYTE(__pdesc, 31, 1)
  98
  99 #define SET_TX_DESC_MACID(__pdesc, __val)               \
 100         SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 7, __val)
 101 #define SET_TX_DESC_QUEUE_SEL(__pdesc, __val)           \
 102         SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val)
 103 #define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val)         \
 104         SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val)
 105 #define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val)        \
 106         SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val)
 107 #define SET_TX_DESC_PIFS(__pdesc, __val)                \
 108         SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val)
 109 #define SET_TX_DESC_RATE_ID(__pdesc, __val)             \
 110         SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 5, __val)
 111 #define SET_TX_DESC_EN_DESC_ID(__pdesc, __val)          \
 112         SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val)
 113 #define SET_TX_DESC_SEC_TYPE(__pdesc, __val)            \
 114         SET_BITS_TO_LE_4BYTE(__pdesc+4, 22, 2, __val)
 115 #define SET_TX_DESC_PKT_OFFSET(__pdesc, __val)          \
 116         SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 5, __val)
 117 #define SET_TX_DESC_MORE_DATA(__pdesc, __val)           \
 118         SET_BITS_TO_LE_4BYTE(__pdesc+4, 29, 1, __val)
 119 #define SET_TX_DESC_TXOP_PS_CAP(__pdesc, __val)         \
 120         SET_BITS_TO_LE_4BYTE(__pdesc+4, 30, 1, __val)
 121 #define SET_TX_DESC_TXOP_PS_MODE(__pdesc, __val)        \
 122         SET_BITS_TO_LE_4BYTE(__pdesc+4, 31, 1, __val)
 123
 124 #define GET_TX_DESC_MACID(__pdesc)                      \
 125         LE_BITS_TO_4BYTE(__pdesc+4, 0, 5)
 126 #define GET_TX_DESC_AGG_ENABLE(__pdesc)                 \
 127         LE_BITS_TO_4BYTE(__pdesc+4, 5, 1)
 128 #define GET_TX_DESC_AGG_BREAK(__pdesc)                  \
 129         LE_BITS_TO_4BYTE(__pdesc+4, 6, 1)
 130 #define GET_TX_DESC_RDG_ENABLE(__pdesc)                 \
 131         LE_BITS_TO_4BYTE(__pdesc+4, 7, 1)
 132 #define GET_TX_DESC_QUEUE_SEL(__pdesc)                  \
 133         LE_BITS_TO_4BYTE(__pdesc+4, 8, 5)
 134 #define GET_TX_DESC_RDG_NAV_EXT(__pdesc)                \
 135         LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
 136 #define GET_TX_DESC_LSIG_TXOP_EN(__pdesc)               \
 137         LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
 138 #define GET_TX_DESC_PIFS(__pdesc)                       \
 139         LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
 140 #define GET_TX_DESC_RATE_ID(__pdesc)                    \
 141         LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
 142 #define GET_TX_DESC_NAV_USE_HDR(__pdesc)                \
 143         LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
 144 #define GET_TX_DESC_EN_DESC_ID(__pdesc)                 \
 145         LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
 146 #define GET_TX_DESC_SEC_TYPE(__pdesc)                   \
 147         LE_BITS_TO_4BYTE(__pdesc+4, 22, 2)
 148 #define GET_TX_DESC_PKT_OFFSET(__pdesc)                 \
 149         LE_BITS_TO_4BYTE(__pdesc+4, 24, 5)
 150
 151 #define SET_TX_DESC_PAID(__pdesc, __val)                \
 152         SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 9, __val)
 153 #define SET_TX_DESC_CCA_RTS(__pdesc, __val)             \
 154         SET_BITS_TO_LE_4BYTE(__pdesc+8, 10, 2, __val)
 155 #define SET_TX_DESC_AGG_ENABLE(__pdesc, __val)          \
 156         SET_BITS_TO_LE_4BYTE(__pdesc+8, 12, 1, __val)
 157 #define SET_TX_DESC_RDG_ENABLE(__pdesc, __val)          \
 158         SET_BITS_TO_LE_4BYTE(__pdesc+8, 13, 1, __val)
 159 #define SET_TX_DESC_NULL_0(__pdesc, __val)              \
 160         SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 1, __val)
 161 #define SET_TX_DESC_NULL_1(__pdesc, __val)              \
 162         SET_BITS_TO_LE_4BYTE(__pdesc+8, 15, 1, __val)
 163 #define SET_TX_DESC_BK(__pdesc, __val)                  \
 164         SET_BITS_TO_LE_4BYTE(__pdesc+8, 16, 1, __val)
 165 #define SET_TX_DESC_MORE_FRAG(__pdesc, __val)           \
 166         SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val)
 167 #define SET_TX_DESC_RAW(__pdesc, __val)                 \
 168         SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val)
 169 #define SET_TX_DESC_SPE_RPT(__pdesc, __val)             \
 170         SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val)
 171 #define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val)       \
 172         SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val)
 173 #define SET_TX_DESC_BT_NULL(__pdesc, __val)             \
 174         SET_BITS_TO_LE_4BYTE(__pdesc+8, 23, 1, __val)
 175 #define SET_TX_DESC_GID(__pdesc, __val)                 \
 176         SET_BITS_TO_LE_4BYTE(__pdesc+8, 24, 6, __val)
 177
 178 #define SET_TX_DESC_WHEADER_LEN(__pdesc, __val)         \
 179         SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 4, __val)
 180 #define SET_TX_DESC_CHK_EN(__pdesc, __val)              \
 181         SET_BITS_TO_LE_4BYTE(__pdesc+12, 4, 1, __val)
 182 #define SET_TX_DESC_EARLY_RATE(__pdesc, __val)          \
 183         SET_BITS_TO_LE_4BYTE(__pdesc+12, 5, 1, __val)
 184 #define SET_TX_DESC_HWSEQ_SEL(__pdesc, __val)           \
 185         SET_BITS_TO_LE_4BYTE(__pdesc+12, 6, 2, __val)
 186 #define SET_TX_DESC_USE_RATE(__pdesc, __val)            \
 187         SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 1, __val)
 188 #define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val)      \
 189         SET_BITS_TO_LE_4BYTE(__pdesc+12, 9, 1, __val)
 190 #define SET_TX_DESC_DISABLE_FB(__pdesc, __val)          \
 191         SET_BITS_TO_LE_4BYTE(__pdesc+12, 10, 1, __val)
 192 #define SET_TX_DESC_CTS2SELF(__pdesc, __val)            \
 193         SET_BITS_TO_LE_4BYTE(__pdesc+12, 11, 1, __val)
 194 #define SET_TX_DESC_RTS_ENABLE(__pdesc, __val)          \
 195         SET_BITS_TO_LE_4BYTE(__pdesc+12, 12, 1, __val)
 196 #define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val)       \
 197         SET_BITS_TO_LE_4BYTE(__pdesc+12, 13, 1, __val)
 198 #define SET_TX_DESC_HW_PORT_ID(__pdesc, __val)          \
 199         SET_BITS_TO_LE_4BYTE(__pdesc+12, 14, 1, __val)
 200 #define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val)         \
 201         SET_BITS_TO_LE_4BYTE(__pdesc+12, 15, 1, __val)
 202 #define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val)         \
 203         SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 1, __val)
 204 #define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val)         \
 205         SET_BITS_TO_LE_4BYTE(__pdesc+12, 17, 5, __val)
 206 #define SET_TX_DESC_NDPA(__pdesc, __val)                \
 207         SET_BITS_TO_LE_4BYTE(__pdesc+12, 22, 2, __val)
 208 #define SET_TX_DESC_AMPDU_MAX_TIME(__pdesc, __val)      \
 209         SET_BITS_TO_LE_4BYTE(__pdesc+12, 24, 8, __val)
 210
 211 /* Dword 4 */
 212 #define SET_TX_DESC_TX_RATE(__pdesc, __val)             \
 213         SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 7, __val)
 214 #define SET_TX_DESC_TRY_RATE(__pdesc, __val)            \
 215         SET_BITS_TO_LE_4BYTE(__pdesc+16, 7, 1, __val)
 216 #define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val)  \
 217         SET_BITS_TO_LE_4BYTE(__pdesc+16, 8, 5, __val)
 218 #define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val)   \
 219         SET_BITS_TO_LE_4BYTE(__pdesc+16, 13, 4, __val)
 220 #define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val)  \
 221         SET_BITS_TO_LE_4BYTE(__pdesc+16, 17, 1, __val)
 222 #define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val)    \
 223         SET_BITS_TO_LE_4BYTE(__pdesc+16, 18, 6, __val)
 224 #define SET_TX_DESC_RTS_RATE(__pdesc, __val)            \
 225         SET_BITS_TO_LE_4BYTE(__pdesc+16, 24, 5, __val)
 226 #define SET_TX_DESC_PCTS_ENABLE(__pdesc, __val)         \
 227         SET_BITS_TO_LE_4BYTE(__pdesc+16, 29, 1, __val)
 228 #define SET_TX_DESC_PCTS_MASK_IDX(__pdesc, __val)       \
 229         SET_BITS_TO_LE_4BYTE(__pdesc+16, 30, 2, __val)
 230
 231 /* Dword 5 */
 232 #define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val)      \
 233         SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 4, __val)
 234 #define SET_TX_DESC_DATA_SHORT(__pdesc, __val)          \
 235         SET_BITS_TO_LE_4BYTE(__pdesc+20, 4, 1, __val)
 236 #define SET_TX_DESC_DATA_BW(__pdesc, __val)             \
 237         SET_BITS_TO_LE_4BYTE(__pdesc+20, 5, 2, __val)
 238 #define SET_TX_DESC_DATA_LDPC(__pdesc, __val)           \
 239         SET_BITS_TO_LE_4BYTE(__pdesc+20, 7, 1, __val)
 240 #define SET_TX_DESC_DATA_STBC(__pdesc, __val)           \
 241         SET_BITS_TO_LE_4BYTE(__pdesc+20, 8, 2, __val)
 242 #define SET_TX_DESC_VCS_STBC(__pdesc, __val)            \
 243         SET_BITS_TO_LE_4BYTE(__pdesc+20, 10, 2, __val)
 244 #define SET_TX_DESC_RTS_SHORT(__pdesc, __val)           \
 245         SET_BITS_TO_LE_4BYTE(__pdesc+20, 12, 1, __val)
 246 #define SET_TX_DESC_RTS_SC(__pdesc, __val)              \
 247         SET_BITS_TO_LE_4BYTE(__pdesc+20, 13, 4, __val)
 248 #define SET_TX_DESC_TX_ANT(__pdesc, __val)              \
 249         SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 4, __val)
 250 #define SET_TX_DESC_TX_POWER_0_PSET(__pdesc, __val)     \
 251         SET_BITS_TO_LE_4BYTE(__pdesc+20, 28, 3, __val)
 252
 253 /* Dword 6 */
 254 #define SET_TX_DESC_SW_DEFINE(__pdesc, __val)           \
 255         SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 12, __val)
 256 #define SET_TX_DESC_ANTSEL_A(__pdesc, __val)            \
 257         SET_BITS_TO_LE_4BYTE(__pdesc+24, 16, 3, __val)
 258 #define SET_TX_DESC_ANTSEL_B(__pdesc, __val)            \
 259         SET_BITS_TO_LE_4BYTE(__pdesc+24, 19, 3, __val)
 260 #define SET_TX_DESC_ANTSEL_C(__pdesc, __val)            \
 261         SET_BITS_TO_LE_4BYTE(__pdesc+24, 22, 3, __val)
 262 #define SET_TX_DESC_ANTSEL_D(__pdesc, __val)            \
 263         SET_BITS_TO_LE_4BYTE(__pdesc+24, 25, 3, __val)
 264
 265 /* Dword 7 */
 266 #define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val)      \
 267         SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 16, __val)
 268 #define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val)       \
 269         SET_BITS_TO_LE_4BYTE(__pdesc+28, 24, 8, __val)
 270
 271 /* Dword 8 */
 272 #define SET_TX_DESC_RTS_RC(__pdesc, __val)              \
 273         SET_BITS_TO_LE_4BYTE(__pdesc+32, 0, 6, __val)
 274 #define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val)          \
 275         SET_BITS_TO_LE_4BYTE(__pdesc+32, 6, 2, __val)
 276 #define SET_TX_DESC_DATA_RC(__pdesc, __val)             \
 277         SET_BITS_TO_LE_4BYTE(__pdesc+32, 8, 6, __val)
 278 #define SET_TX_DESC_ENABLE_HW_SELECT(__pdesc, __val)    \
 279         SET_BITS_TO_LE_4BYTE(__pdesc+32, 15, 1, __val)
 280 #define SET_TX_DESC_NEXT_HEAD_PAGE(__pdesc, __val)      \
 281         SET_BITS_TO_LE_4BYTE(__pdesc+32, 16, 8, __val)
 282 #define SET_TX_DESC_TAIL_PAGE(__pdesc, __val)           \
 283         SET_BITS_TO_LE_4BYTE(__pdesc+32, 24, 8, __val)
 284
 285 /* Dword 9 */
 286 #define SET_TX_DESC_PADDING_LENGTH(__pdesc, __val)      \
 287         SET_BITS_TO_LE_4BYTE(__pdesc+36, 0, 11, __val)
 288 #define SET_TX_DESC_TXBF_PATH(__pdesc, __val)           \
 289         SET_BITS_TO_LE_4BYTE(__pdesc+36, 11, 1, __val)
 290 #define SET_TX_DESC_SEQ(__pdesc, __val)                 \
 291         SET_BITS_TO_LE_4BYTE(__pdesc+36, 12, 12, __val)
 292 #define SET_TX_DESC_FINAL_DATA_RATE(__pdesc, __val)     \
 293         SET_BITS_TO_LE_4BYTE(__pdesc+36, 24, 8, __val)
 294
 295 /* Dword 10 */
 296 #define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val)   \
 297         SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
 298
 299 /* Dword 11*/
 300 #define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val)   \
 301         SET_BITS_TO_LE_4BYTE(__pdesc+48, 0, 32, __val)
 302
 303 #define SET_EARLYMODE_PKTNUM(__paddr, __val)            \
 304         SET_BITS_TO_LE_4BYTE(__paddr, 0, 4, __val)
 305 #define SET_EARLYMODE_LEN0(__paddr, __val)              \
 306         SET_BITS_TO_LE_4BYTE(__paddr, 4, 15, __val)
 307 #define SET_EARLYMODE_LEN1(__paddr, __val)              \
 308         SET_BITS_TO_LE_4BYTE(__paddr, 16, 2, __val)
 309 #define SET_EARLYMODE_LEN1_1(__paddr, __val)            \
 310         SET_BITS_TO_LE_4BYTE(__paddr, 19, 13, __val)
 311 #define SET_EARLYMODE_LEN1_2(__paddr, __val)            \
 312         SET_BITS_TO_LE_4BYTE(__paddr+4, 0, 2, __val)
 313 #define SET_EARLYMODE_LEN2(__paddr, __val)              \
 314         SET_BITS_TO_LE_4BYTE(__paddr+4, 2, 15,  __val)
 315 #define SET_EARLYMODE_LEN2_1(__paddr, __val)            \
 316         SET_BITS_TO_LE_4BYTE(__paddr, 2, 4,  __val)
 317 #define SET_EARLYMODE_LEN2_2(__paddr, __val)            \
 318         SET_BITS_TO_LE_4BYTE(__paddr+4, 0, 8,  __val)
 319 #define SET_EARLYMODE_LEN3(__paddr, __val)              \
 320         SET_BITS_TO_LE_4BYTE(__paddr+4, 17, 15, __val)
 321 #define SET_EARLYMODE_LEN4(__paddr, __val)              \
 322         SET_BITS_TO_LE_4BYTE(__paddr+4, 20, 12, __val)
 323
 324 /* TX/RX buffer descriptor */
 325
 326 #define SET_TX_EXTBUFF_DESC_LEN(__pdesc, __val, __set)  \
 327         SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16), 0, 16, __val)
 328 #define SET_TX_EXTBUFF_DESC_ADDR_LOW(__pdesc, __val, __set)\
 329         SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16)+4, 0, 32, __val)
 330 #define SET_TX_EXTBUFF_DESC_ADDR_HIGH(__pdesc, __val, __set)\
 331         SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16)+8, 0, 32, __val)
 332
 333 /* for Txfilldescroptor92ee, fill the desc content. */
 334 #if (DMA_IS_64BIT == 1)
 335 #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pdesc, __offset, __val)     \
 336         SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16), 0, 16, __val)
 337 #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pdesc, __offset, __val)   \
 338         SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16), 31, 1, __val)
 339 #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pdesc, __offset, __val) \
 340         SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16)+4, 0, 32, __val)
 341 #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pdesc, __offset, __val)\
 342         SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*16)+8, 0, 32, __val)
 343 #define GET_TXBUFFER_DESC_ADDR_LOW(__pdesc, __offset)                   \
 344         LE_BITS_TO_4BYTE(__pdesc+(__offset*16)+4, 0, 32)
 345 #else
 346 #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pdesc, __offset, __val)     \
 347         SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8), 0, 16, __val)
 348 #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pdesc, __offset, __val)   \
 349         SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8), 31, 1, __val)
 350 #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pdesc, __offset, __val) \
 351         SET_BITS_TO_LE_4BYTE(__pdesc+(__offset*8)+4, 0, 32, __val)
 352 #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pdesc, __offset, __val)
 353 #define GET_TXBUFFER_DESC_ADDR_LOW(__pdesc, __offset)                   \
 354         LE_BITS_TO_4BYTE(__pdesc+(__offset*8)+4, 0, 32)
 355 #endif
 356
 357 /* Dword 0 */
 358 #define SET_TX_BUFF_DESC_LEN_0(__pdesc, __val)          \
 359         SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
 360 #define SET_TX_BUFF_DESC_PSB(__pdesc, __val)            \
 361         SET_BITS_TO_LE_4BYTE(__pdesc, 16, 15, __val)
 362 #define SET_TX_BUFF_DESC_OWN(__pdesc, __val)            \
 363         SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
 364
 365 /* Dword 1 */
 366 #define SET_TX_BUFF_DESC_ADDR_LOW_0(__pdesc, __val)     \
 367         SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 32, __val)
 368 #if (DMA_IS_64BIT == 1)
 369 /* Dword 2 */
 370 #define SET_TX_BUFF_DESC_ADDR_HIGH_0(__pdesc, __val)    \
 371         SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 32, __val)
 372 /* Dword 3 / RESERVED 0 */
 373 /* Dword 4 */
 374 #define SET_TX_BUFF_DESC_LEN_1(__pdesc, __val)          \
 375         SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 16, __val)
 376 #define SET_TX_BUFF_DESC_AMSDU_1(__pdesc, __val)        \
 377         SET_BITS_TO_LE_4BYTE(__pdesc+16, 31, 1, __val)
 378 /* Dword 5 */
 379 #define SET_TX_BUFF_DESC_ADDR_LOW_1(__pdesc, __val)     \
 380         SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 32, __val)
 381 /* Dword 6 */
 382 #define SET_TX_BUFF_DESC_ADDR_HIGH_1(__pdesc, __val)    \
 383         SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
 384 /* Dword 7 / RESERVED 0 */
 385 /* Dword 8 */
 386 #define SET_TX_BUFF_DESC_LEN_2(__pdesc, __val)          \
 387         SET_BITS_TO_LE_4BYTE(__pdesc+32, 0, 16, __val)
 388 #define SET_TX_BUFF_DESC_AMSDU_2(__pdesc, __val)        \
 389         SET_BITS_TO_LE_4BYTE(__pdesc+32, 31, 1, __val)
 390 /* Dword 9 */
 391 #define SET_TX_BUFF_DESC_ADDR_LOW_2(__pdesc, __val)     \
 392         SET_BITS_TO_LE_4BYTE(__pdesc+36, 0, 32, __val)
 393 /* Dword 10 */
 394 #define SET_TX_BUFF_DESC_ADDR_HIGH_2(__pdesc, __val)    \
 395         SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
 396 /* Dword 11 / RESERVED 0 */
 397 /* Dword 12 */
 398 #define SET_TX_BUFF_DESC_LEN_3(__pdesc, __val)          \
 399         SET_BITS_TO_LE_4BYTE(__pdesc+48, 0, 16, __val)
 400 #define SET_TX_BUFF_DESC_AMSDU_3(__pdesc, __val)        \
 401         SET_BITS_TO_LE_4BYTE(__pdesc+48, 31, 1, __val)
 402 /* Dword 13 */
 403 #define SET_TX_BUFF_DESC_ADDR_LOW_3(__pdesc, __val)     \
 404         SET_BITS_TO_LE_4BYTE(__pdesc+52, 0, 32, __val)
 405 /* Dword 14 */
 406 #define SET_TX_BUFF_DESC_ADDR_HIGH_3(__pdesc, __val)    \
 407         SET_BITS_TO_LE_4BYTE(__pdesc+56, 0, 32, __val)
 408 /* Dword 15 / RESERVED 0 */
 409 #else
 410 #define SET_TX_BUFF_DESC_ADDR_HIGH_0(__pdesc, __val)
 411 /* Dword 2 */
 412 #define SET_TX_BUFF_DESC_LEN_1(__pdesc, __val)          \
 413         SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 16, __val)
 414 #define SET_TX_BUFF_DESC_AMSDU_1(__pdesc, __val)        \
 415         SET_BITS_TO_LE_4BYTE(__pdesc+8, 31, 1, __val)
 416 /* Dword 3 */
 417 #define SET_TX_BUFF_DESC_ADDR_LOW_1(__pdesc, __val)     \
 418         SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 32, __val)
 419 #define SET_TX_BUFF_DESC_ADDR_HIGH_1(__pdesc, __val)
 420 /* Dword 4 */
 421 #define SET_TX_BUFF_DESC_LEN_2(__pdesc, __val)          \
 422         SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 16, __val)
 423 #define SET_TX_BUFF_DESC_AMSDU_2(__pdesc, __val)        \
 424         SET_BITS_TO_LE_4BYTE(__pdesc+16, 31, 1, __val)
 425 /* Dword 5 */
 426 #define SET_TX_BUFF_DESC_ADDR_LOW_2(__pdesc, __val)     \
 427         SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 32, __val)
 428 #define SET_TX_BUFF_DESC_ADDR_HIGH_2(__pdesc, __val)
 429 /* Dword 6 */
 430 #define SET_TX_BUFF_DESC_LEN_3(__pdesc, __val)          \
 431         SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 16, __val)
 432 #define SET_TX_BUFF_DESC_AMSDU_3(__pdesc, __val)        \
 433         SET_BITS_TO_LE_4BYTE(__pdesc+24, 31, 1, __val)
 434 /* Dword 7 */
 435 #define SET_TX_BUFF_DESC_ADDR_LOW_3(__pdesc, __val)     \
 436         SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
 437 #define SET_TX_BUFF_DESC_ADDR_HIGH_3(__pdesc, __val)
 438 #endif
 439
 440 /* RX buffer  */
 441
 442 /* DWORD 0 */
 443 #define SET_RX_BUFFER_DESC_DATA_LENGTH(__status, __val) \
 444         SET_BITS_TO_LE_4BYTE(__status, 0, 14, __val)
 445 #define SET_RX_BUFFER_DESC_LS(__status, __val)          \
 446         SET_BITS_TO_LE_4BYTE(__status, 15, 1, __val)
 447 #define SET_RX_BUFFER_DESC_FS(__status, __val)          \
 448         SET_BITS_TO_LE_4BYTE(__status, 16, 1, __val)
 449 #define SET_RX_BUFFER_DESC_TOTAL_LENGTH(__status, __val)        \
 450         SET_BITS_TO_LE_4BYTE(__status, 16, 15, __val)
 451
 452 #define GET_RX_BUFFER_DESC_OWN(__status)                        \
 453         LE_BITS_TO_4BYTE(__status, 31, 1)
 454 #define GET_RX_BUFFER_DESC_LS(__status)                 \
 455         LE_BITS_TO_4BYTE(__status, 15, 1)
 456 #define GET_RX_BUFFER_DESC_FS(__status)                 \
 457         LE_BITS_TO_4BYTE(__status, 16, 1)
 458 #define GET_RX_BUFFER_DESC_TOTAL_LENGTH(__status)       \
 459         LE_BITS_TO_4BYTE(__status, 16, 15)
 460
 461 /* DWORD 1 */
 462 #define SET_RX_BUFFER_PHYSICAL_LOW(__status, __val)     \
 463         SET_BITS_TO_LE_4BYTE(__status+4, 0, 32, __val)
 464
 465 /* DWORD 2 */
 466 #define SET_RX_BUFFER_PHYSICAL_HIGH(__status, __val)    \
 467         SET_BITS_TO_LE_4BYTE(__status+8, 0, 32, __val)
 468
 469 #define GET_RX_DESC_PKT_LEN(__pdesc)                    \
 470         LE_BITS_TO_4BYTE(__pdesc, 0, 14)
 471 #define GET_RX_DESC_CRC32(__pdesc)                      \
 472         LE_BITS_TO_4BYTE(__pdesc, 14, 1)
 473 #define GET_RX_DESC_ICV(__pdesc)                        \
 474         LE_BITS_TO_4BYTE(__pdesc, 15, 1)
 475 #define GET_RX_DESC_DRV_INFO_SIZE(__pdesc)              \
 476         LE_BITS_TO_4BYTE(__pdesc, 16, 4)
 477 #define GET_RX_DESC_SECURITY(__pdesc)                   \
 478         LE_BITS_TO_4BYTE(__pdesc, 20, 3)
 479 #define GET_RX_DESC_QOS(__pdesc)                        \
 480         LE_BITS_TO_4BYTE(__pdesc, 23, 1)
 481 #define GET_RX_DESC_SHIFT(__pdesc)                      \
 482         LE_BITS_TO_4BYTE(__pdesc, 24, 2)
 483 #define GET_RX_DESC_PHYST(__pdesc)                      \
 484         LE_BITS_TO_4BYTE(__pdesc, 26, 1)
 485 #define GET_RX_DESC_SWDEC(__pdesc)                      \
 486         LE_BITS_TO_4BYTE(__pdesc, 27, 1)
 487 #define GET_RX_DESC_LS(__pdesc)                         \
 488         LE_BITS_TO_4BYTE(__pdesc, 28, 1)
 489 #define GET_RX_DESC_FS(__pdesc)                         \
 490         LE_BITS_TO_4BYTE(__pdesc, 29, 1)
 491 #define GET_RX_DESC_EOR(__pdesc)                        \
 492         LE_BITS_TO_4BYTE(__pdesc, 30, 1)
 493 #define GET_RX_DESC_OWN(__pdesc)                        \
 494         LE_BITS_TO_4BYTE(__pdesc, 31, 1)
 495
 496 #define SET_RX_DESC_PKT_LEN(__pdesc, __val)             \
 497         SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
 498 #define SET_RX_DESC_EOR(__pdesc, __val)                 \
 499         SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
 500 #define SET_RX_DESC_OWN(__pdesc, __val)                 \
 501         SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
 502
 503 #define GET_RX_DESC_MACID(__pdesc)                      \
 504         LE_BITS_TO_4BYTE(__pdesc+4, 0, 7)
 505 #define GET_RX_DESC_TID(__pdesc)                        \
 506         LE_BITS_TO_4BYTE(__pdesc+4, 8, 4)
 507 #define GET_RX_DESC_MACID_VLD(__pdesc)                  \
 508         LE_BITS_TO_4BYTE(__pdesc+4, 12, 1)
 509 #define GET_RX_DESC_AMSDU(__pdesc)                      \
 510         LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
 511 #define GET_RX_DESC_RXID_MATCH(__pdesc)                 \
 512         LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
 513 #define GET_RX_DESC_PAGGR(__pdesc)                      \
 514         LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
 515 #define GET_RX_DESC_A1_FIT(__pdesc)                     \
 516         LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
 517 #define GET_RX_DESC_TCPOFFLOAD_CHKERR(__pdesc)          \
 518         LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
 519 #define GET_RX_DESC_TCPOFFLOAD_IPVER(__pdesc)           \
 520         LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
 521 #define GET_RX_DESC_TCPOFFLOAD_IS_TCPUDP(__pdesc)       \
 522         LE_BITS_TO_4BYTE(__pdesc+4, 22, 1)
 523 #define GET_RX_DESC_TCPOFFLOAD_CHK_VLD(__pdesc)         \
 524         LE_BITS_TO_4BYTE(__pdesc+4, 23, 1)
 525 #define GET_RX_DESC_PAM(__pdesc)                        \
 526         LE_BITS_TO_4BYTE(__pdesc+4, 24, 1)
 527 #define GET_RX_DESC_PWR(__pdesc)                        \
 528         LE_BITS_TO_4BYTE(__pdesc+4, 25, 1)
 529 #define GET_RX_DESC_MD(__pdesc)                         \
 530         LE_BITS_TO_4BYTE(__pdesc+4, 26, 1)
 531 #define GET_RX_DESC_MF(__pdesc)                         \
 532         LE_BITS_TO_4BYTE(__pdesc+4, 27, 1)
 533 #define GET_RX_DESC_TYPE(__pdesc)                       \
 534         LE_BITS_TO_4BYTE(__pdesc+4, 28, 2)
 535 #define GET_RX_DESC_MC(__pdesc)                         \
 536         LE_BITS_TO_4BYTE(__pdesc+4, 30, 1)
 537 #define GET_RX_DESC_BC(__pdesc)                         \
 538         LE_BITS_TO_4BYTE(__pdesc+4, 31, 1)
 539 #define GET_RX_DESC_SEQ(__pdesc)                        \
 540         LE_BITS_TO_4BYTE(__pdesc+8, 0, 12)
 541 #define GET_RX_DESC_FRAG(__pdesc)                       \
 542         LE_BITS_TO_4BYTE(__pdesc+8, 12, 4)
 543 #define GET_RX_DESC_RX_IS_QOS(__pdesc)                  \
 544         LE_BITS_TO_4BYTE(__pdesc+8, 16, 1)
 545 #define GET_RX_STATUS_DESC_RPT_SEL(__pdesc)             \
 546         LE_BITS_TO_4BYTE(__pdesc+8, 28, 1)
 547
 548 #define GET_RX_DESC_RXMCS(__pdesc)                      \
 549         LE_BITS_TO_4BYTE(__pdesc+12, 0, 7)
 550 #define GET_RX_DESC_HTC(__pdesc)                        \
 551         LE_BITS_TO_4BYTE(__pdesc+12, 10, 1)
 552 #define GET_RX_STATUS_DESC_EOSP(__pdesc)                \
 553         LE_BITS_TO_4BYTE(__pdesc+12, 11, 1)
 554 #define GET_RX_STATUS_DESC_BSSID_FIT(__pdesc)           \
 555         LE_BITS_TO_4BYTE(__pdesc+12, 12, 2)
 556 #define GET_RX_STATUS_DESC_DMA_AGG_NUM(__pdesc)         \
 557         LE_BITS_TO_4BYTE(__pdesc+12, 16, 8)
 558 #define GET_RX_STATUS_DESC_PATTERN_MATCH(__pdesc)       \
 559         LE_BITS_TO_4BYTE(__pdesc+12, 29, 1)
 560 #define GET_RX_STATUS_DESC_UNICAST_MATCH(__pdesc)       \
 561         LE_BITS_TO_4BYTE(__pdesc+12, 30, 1)
 562 #define GET_RX_STATUS_DESC_MAGIC_MATCH(__pdesc)         \
 563         LE_BITS_TO_4BYTE(__pdesc+12, 31, 1)
 564
 565 #define GET_RX_DESC_TSFL(__pdesc)                       \
 566         LE_BITS_TO_4BYTE(__pdesc+20, 0, 32)
 567
 568 #define GET_RX_DESC_BUFF_ADDR(__pdesc)                  \
 569         LE_BITS_TO_4BYTE(__pdesc+24, 0, 32)
 570 #define GET_RX_DESC_BUFF_ADDR64(__pdesc)                \
 571         LE_BITS_TO_4BYTE(__pdesc+28, 0, 32)
 572
 573 #define SET_RX_DESC_BUFF_ADDR(__pdesc, __val)           \
 574         SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
 575 #define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val)         \
 576         SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
 577
 578 /* TX report 2 format in Rx desc*/
 579
 580 #define GET_RX_RPT2_DESC_PKT_LEN(__status)      \
 581         LE_BITS_TO_4BYTE(__status, 0, 9)
 582 #define GET_RX_RPT2_DESC_MACID_VALID_1(__status)        \
 583         LE_BITS_TO_4BYTE(__status+16, 0, 32)
 584 #define GET_RX_RPT2_DESC_MACID_VALID_2(__status)        \
 585         LE_BITS_TO_4BYTE(__status+20, 0, 32)
 586
 587 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size)               \
 588 do {                                                            \
 589         if (_size > TX_DESC_NEXT_DESC_OFFSET)                   \
 590                 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET);   \
 591         else                                                    \
 592                 memset(__pdesc, 0, _size);                      \
 593 } while (0)
 594
 595 #define RTL92EE_RX_HAL_IS_CCK_RATE(rxmcs)\
 596         (rxmcs == DESC_RATE1M ||\
 597          rxmcs == DESC_RATE2M ||\
 598          rxmcs == DESC_RATE5_5M ||\
 599          rxmcs == DESC_RATE11M)
 600
 601 #define IS_LITTLE_ENDIAN        1
 602
 603 struct phy_rx_agc_info_t {
 604         #if IS_LITTLE_ENDIAN
 605                 u8 gain:7, trsw:1;
 606         #else
 607                 u8 trsw:1, gain:7;
 608         #endif
 609 };
 610
 611 struct phy_status_rpt {
 612         struct phy_rx_agc_info_t path_agc[2];
 613         u8 ch_corr[2];
 614         u8 cck_sig_qual_ofdm_pwdb_all;
 615         u8 cck_agc_rpt_ofdm_cfosho_a;
 616         u8 cck_rpt_b_ofdm_cfosho_b;
 617         u8 rsvd_1;
 618         u8 noise_power_db_msb;
 619         u8 path_cfotail[2];
 620         u8 pcts_mask[2];
 621         u8 stream_rxevm[2];
 622         u8 path_rxsnr[2];
 623         u8 noise_power_db_lsb;
 624         u8 rsvd_2[3];
 625         u8 stream_csi[2];
 626         u8 stream_target_csi[2];
 627         u8 sig_evm;
 628         u8 rsvd_3;
 629 #if IS_LITTLE_ENDIAN
 630         u8 antsel_rx_keep_2:1;  /*ex_intf_flg:1;*/
 631         u8 sgi_en:1;
 632         u8 rxsc:2;
 633         u8 idle_long:1;
 634         u8 r_ant_train_en:1;
 635         u8 ant_sel_b:1;
 636         u8 ant_sel:1;
 637 #else   /* _BIG_ENDIAN_ */
 638         u8 ant_sel:1;
 639         u8 ant_sel_b:1;
 640         u8 r_ant_train_en:1;
 641         u8 idle_long:1;
 642         u8 rxsc:2;
 643         u8 sgi_en:1;
 644         u8 antsel_rx_keep_2:1;  /*ex_intf_flg:1;*/
 645 #endif
 646 } __packed;
 647
 648 struct rx_fwinfo {
 649         u8 gain_trsw[4];
 650         u8 pwdb_all;
 651         u8 cfosho[4];
 652         u8 cfotail[4];
 653         char rxevm[2];
 654         char rxsnr[4];
 655         u8 pdsnr[2];
 656         u8 csi_current[2];
 657         u8 csi_target[2];
 658         u8 sigevm;
 659         u8 max_ex_pwr;
 660         u8 ex_intf_flag:1;
 661         u8 sgi_en:1;
 662         u8 rxsc:2;
 663         u8 reserve:4;
 664 } __packed;
 665
 666 struct tx_desc {
 667         u32 pktsize:16;
 668         u32 offset:8;
 669         u32 bmc:1;
 670         u32 htc:1;
 671         u32 lastseg:1;
 672         u32 firstseg:1;
 673         u32 linip:1;
 674         u32 noacm:1;
 675         u32 gf:1;
 676         u32 own:1;
 677
 678         u32 macid:6;
 679         u32 rsvd0:2;
 680         u32 queuesel:5;
 681         u32 rd_nav_ext:1;
 682         u32 lsig_txop_en:1;
 683         u32 pifs:1;
 684         u32 rateid:4;
 685         u32 nav_usehdr:1;
 686         u32 en_descid:1;
 687         u32 sectype:2;
 688         u32 pktoffset:8;
 689
 690         u32 rts_rc:6;
 691         u32 data_rc:6;
 692         u32 agg_en:1;
 693         u32 rdg_en:1;
 694         u32 bar_retryht:2;
 695         u32 agg_break:1;
 696         u32 morefrag:1;
 697         u32 raw:1;
 698         u32 ccx:1;
 699         u32 ampdudensity:3;
 700         u32 bt_int:1;
 701         u32 ant_sela:1;
 702         u32 ant_selb:1;
 703         u32 txant_cck:2;
 704         u32 txant_l:2;
 705         u32 txant_ht:2;
 706
 707         u32 nextheadpage:8;
 708         u32 tailpage:8;
 709         u32 seq:12;
 710         u32 cpu_handle:1;
 711         u32 tag1:1;
 712         u32 trigger_int:1;
 713         u32 hwseq_en:1;
 714
 715         u32 rtsrate:5;
 716         u32 apdcfe:1;
 717         u32 qos:1;
 718         u32 hwseq_ssn:1;
 719         u32 userrate:1;
 720         u32 dis_rtsfb:1;
 721         u32 dis_datafb:1;
 722         u32 cts2self:1;
 723         u32 rts_en:1;
 724         u32 hwrts_en:1;
 725         u32 portid:1;
 726         u32 pwr_status:3;
 727         u32 waitdcts:1;
 728         u32 cts2ap_en:1;
 729         u32 txsc:2;
 730         u32 stbc:2;
 731         u32 txshort:1;
 732         u32 txbw:1;
 733         u32 rtsshort:1;
 734         u32 rtsbw:1;
 735         u32 rtssc:2;
 736         u32 rtsstbc:2;
 737
 738         u32 txrate:6;
 739         u32 shortgi:1;
 740         u32 ccxt:1;
 741         u32 txrate_fb_lmt:5;
 742         u32 rtsrate_fb_lmt:4;
 743         u32 retrylmt_en:1;
 744         u32 txretrylmt:6;
 745         u32 usb_txaggnum:8;
 746
 747         u32 txagca:5;
 748         u32 txagcb:5;
 749         u32 usemaxlen:1;
 750         u32 maxaggnum:5;
 751         u32 mcsg1maxlen:4;
 752         u32 mcsg2maxlen:4;
 753         u32 mcsg3maxlen:4;
 754         u32 mcs7sgimaxlen:4;
 755
 756         u32 txbuffersize:16;
 757         u32 sw_offset30:8;
 758         u32 sw_offset31:4;
 759         u32 rsvd1:1;
 760         u32 antsel_c:1;
 761         u32 null_0:1;
 762         u32 null_1:1;
 763
 764         u32 txbuffaddr;
 765         u32 txbufferaddr64;
 766         u32 nextdescaddress;
 767         u32 nextdescaddress64;
 768
 769         u32 reserve_pass_pcie_mm_limit[4];
 770 } __packed;
 771
 772 struct rx_desc {
 773         u32 length:14;
 774         u32 crc32:1;
 775         u32 icverror:1;
 776         u32 drv_infosize:4;
 777         u32 security:3;
 778         u32 qos:1;
 779         u32 shift:2;
 780         u32 phystatus:1;
 781         u32 swdec:1;
 782         u32 lastseg:1;
 783         u32 firstseg:1;
 784         u32 eor:1;
 785         u32 own:1;
 786
 787         u32 macid:6;
 788         u32 tid:4;
 789         u32 hwrsvd:5;
 790         u32 paggr:1;
 791         u32 faggr:1;
 792         u32 a1_fit:4;
 793         u32 a2_fit:4;
 794         u32 pam:1;
 795         u32 pwr:1;
 796         u32 moredata:1;
 797         u32 morefrag:1;
 798         u32 type:2;
 799         u32 mc:1;
 800         u32 bc:1;
 801
 802         u32 seq:12;
 803         u32 frag:4;
 804         u32 nextpktlen:14;
 805         u32 nextind:1;
 806         u32 rsvd:1;
 807
 808         u32 rxmcs:6;
 809         u32 rxht:1;
 810         u32 amsdu:1;
 811         u32 splcp:1;
 812         u32 bandwidth:1;
 813         u32 htc:1;
 814         u32 tcpchk_rpt:1;
 815         u32 ipcchk_rpt:1;
 816         u32 tcpchk_valid:1;
 817         u32 hwpcerr:1;
 818         u32 hwpcind:1;
 819         u32 iv0:16;
 820
 821         u32 iv1;
 822
 823         u32 tsfl;
 824
 825         u32 bufferaddress;
 826         u32 bufferaddress64;
 827
 828 } __packed;
 829
 830 void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
 831                              u8 queue_index);
 832 u16     rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw,
 833                                           u8 queue_index);
 834 u16 rtl92ee_get_available_desc(struct ieee80211_hw *hw, u8 queue_index);
 835 void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
 836                                  u8 *tx_bd_desc, u8 *desc, u8 queue_index,
 837                                  struct sk_buff *skb, dma_addr_t addr);
 838
 839 void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw,
 840                           struct ieee80211_hdr *hdr, u8 *pdesc_tx,
 841                           u8 *pbd_desc_tx,
 842                           struct ieee80211_tx_info *info,
 843                           struct ieee80211_sta *sta,
 844                           struct sk_buff *skb,
 845                           u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
 846 bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,
 847                            struct rtl_stats *status,
 848                            struct ieee80211_rx_status *rx_status,
 849                            u8 *pdesc, struct sk_buff *skb);
 850 void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
 851                       u8 desc_name, u8 *val);
 852
 853 u32 rtl92ee_get_desc(u8 *pdesc, bool istx, u8 desc_name);
 854 bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index);
 855 void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
 856 void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
 857                              bool firstseg, bool lastseg,
 858                              struct sk_buff *skb);
 859 u32 rtl92ee_rx_command_packet(struct ieee80211_hw *hw,
 860                               struct rtl_stats status,
 861                               struct sk_buff *skb);
 862 #endif