drivers/net/wireless/rtlwifi/rtl8192se/def.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29 #ifndef __REALTEK_92S_DEF_H__
  30 #define __REALTEK_92S_DEF_H__
  31
  32 #define RX_MPDU_QUEUE                           0
  33 #define RX_CMD_QUEUE                            1
  34 #define RX_MAX_QUEUE                            2
  35
  36 #define SHORT_SLOT_TIME                         9
  37 #define NON_SHORT_SLOT_TIME                     20
  38
  39 /* Queue Select Value in TxDesc */
  40 #define QSLT_BK                                 0x2
  41 #define QSLT_BE                                 0x0
  42 #define QSLT_VI                                 0x5
  43 #define QSLT_VO                                 0x6
  44 #define QSLT_BEACON                             0x10
  45 #define QSLT_HIGH                               0x11
  46 #define QSLT_MGNT                               0x12
  47 #define QSLT_CMD                                0x13
  48
  49 /* Tx Desc */
  50 #define TX_DESC_SIZE_RTL8192S                   (16 * 4)
  51 #define TX_CMDDESC_SIZE_RTL8192S                (16 * 4)
  52
  53 /* Define a macro that takes a le32 word, converts it to host ordering,
  54  * right shifts by a specified count, creates a mask of the specified
  55  * bit count, and extracts that number of bits.
  56  */
  57
  58 #define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask)             \
  59         ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
  60         BIT_LEN_MASK_32(__mask))
  61
  62 /* Define a macro that clears a bit field in an le32 word and
  63  * sets the specified value into that bit field. The resulting
  64  * value remains in le32 ordering; however, it is properly converted
  65  * to host ordering for the clear and set operations before conversion
  66  * back to le32.
  67  */
  68
  69 #define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val)      \
  70         (*(__le32 *)(__pdesc) =                                 \
  71         (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) &     \
  72         (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) |        \
  73         (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
  74
  75 /* macros to read/write various fields in RX or TX descriptors */
  76
  77 /* Dword 0 */
  78 #define SET_TX_DESC_PKT_SIZE(__pdesc, __val)                    \
  79         SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
  80 #define SET_TX_DESC_OFFSET(__pdesc, __val)                      \
  81         SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
  82 #define SET_TX_DESC_TYPE(__pdesc, __val)                        \
  83         SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val)
  84 #define SET_TX_DESC_LAST_SEG(__pdesc, __val)                    \
  85         SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
  86 #define SET_TX_DESC_FIRST_SEG(__pdesc, __val)                   \
  87         SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
  88 #define SET_TX_DESC_LINIP(__pdesc, __val)                       \
  89         SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
  90 #define SET_TX_DESC_AMSDU(__pdesc, __val)                       \
  91         SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
  92 #define SET_TX_DESC_GREEN_FIELD(__pdesc, __val)                 \
  93         SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
  94 #define SET_TX_DESC_OWN(__pdesc, __val)                         \
  95         SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
  96
  97 #define GET_TX_DESC_OWN(__pdesc)                                \
  98         SHIFT_AND_MASK_LE(__pdesc, 31, 1)
  99
 100 /* Dword 1 */
 101 #define SET_TX_DESC_MACID(__pdesc, __val)                       \
 102         SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val)
 103 #define SET_TX_DESC_MORE_DATA(__pdesc, __val)                   \
 104         SET_BITS_OFFSET_LE(__pdesc + 4, 5, 1, __val)
 105 #define SET_TX_DESC_MORE_FRAG(__pdesc, __val)                   \
 106         SET_BITS_OFFSET_LE(__pdesc + 4, 6, 1, __val)
 107 #define SET_TX_DESC_PIFS(__pdesc, __val)                        \
 108         SET_BITS_OFFSET_LE(__pdesc + 4, 7, 1, __val)
 109 #define SET_TX_DESC_QUEUE_SEL(__pdesc, __val)                   \
 110         SET_BITS_OFFSET_LE(__pdesc + 4, 8, 5, __val)
 111 #define SET_TX_DESC_ACK_POLICY(__pdesc, __val)                  \
 112         SET_BITS_OFFSET_LE(__pdesc + 4, 13, 2, __val)
 113 #define SET_TX_DESC_NO_ACM(__pdesc, __val)                      \
 114         SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val)
 115 #define SET_TX_DESC_NON_QOS(__pdesc, __val)                     \
 116         SET_BITS_OFFSET_LE(__pdesc + 4, 16, 1, __val)
 117 #define SET_TX_DESC_KEY_ID(__pdesc, __val)                      \
 118         SET_BITS_OFFSET_LE(__pdesc + 4, 17, 2, __val)
 119 #define SET_TX_DESC_OUI(__pdesc, __val)                         \
 120         SET_BITS_OFFSET_LE(__pdesc + 4, 19, 1, __val)
 121 #define SET_TX_DESC_PKT_TYPE(__pdesc, __val)                    \
 122         SET_BITS_OFFSET_LE(__pdesc + 4, 20, 1, __val)
 123 #define SET_TX_DESC_EN_DESC_ID(__pdesc, __val)                  \
 124         SET_BITS_OFFSET_LE(__pdesc + 4, 21, 1, __val)
 125 #define SET_TX_DESC_SEC_TYPE(__pdesc, __val)                    \
 126         SET_BITS_OFFSET_LE(__pdesc + 4, 22, 2, __val)
 127 #define SET_TX_DESC_WDS(__pdesc, __val)                         \
 128         SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val)
 129 #define SET_TX_DESC_HTC(__pdesc, __val)                         \
 130         SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val)
 131 #define SET_TX_DESC_PKT_OFFSET(__pdesc, __val)                  \
 132         SET_BITS_OFFSET_LE(__pdesc + 4, 26, 5, __val)
 133 #define SET_TX_DESC_HWPC(__pdesc, __val)                        \
 134         SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val)
 135
 136 /* Dword 2 */
 137 #define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val)            \
 138         SET_BITS_OFFSET_LE(__pdesc + 8, 0, 6, __val)
 139 #define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val)          \
 140         SET_BITS_OFFSET_LE(__pdesc + 8, 6, 1, __val)
 141 #define SET_TX_DESC_TSFL(__pdesc, __val)                        \
 142         SET_BITS_OFFSET_LE(__pdesc + 8, 7, 5, __val)
 143 #define SET_TX_DESC_RTS_RETRY_COUNT(__pdesc, __val)             \
 144         SET_BITS_OFFSET_LE(__pdesc + 8, 12, 6, __val)
 145 #define SET_TX_DESC_DATA_RETRY_COUNT(__pdesc, __val)            \
 146         SET_BITS_OFFSET_LE(__pdesc + 8, 18, 6, __val)
 147 #define SET_TX_DESC_RSVD_MACID(__pdesc, __val)                  \
 148         SET_BITS_OFFSET_LE(((__pdesc) + 8), 24, 5, __val)
 149 #define SET_TX_DESC_AGG_ENABLE(__pdesc, __val)                  \
 150         SET_BITS_OFFSET_LE(__pdesc + 8, 29, 1, __val)
 151 #define SET_TX_DESC_AGG_BREAK(__pdesc, __val)                   \
 152         SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val)
 153 #define SET_TX_DESC_OWN_MAC(__pdesc, __val)                     \
 154         SET_BITS_OFFSET_LE(__pdesc + 8, 31, 1, __val)
 155
 156 /* Dword 3 */
 157 #define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val)              \
 158         SET_BITS_OFFSET_LE(__pdesc + 12, 0, 8, __val)
 159 #define SET_TX_DESC_TAIL_PAGE(__pdesc, __val)                   \
 160         SET_BITS_OFFSET_LE(__pdesc + 12, 8, 8, __val)
 161 #define SET_TX_DESC_SEQ(__pdesc, __val)                         \
 162         SET_BITS_OFFSET_LE(__pdesc + 12, 16, 12, __val)
 163 #define SET_TX_DESC_FRAG(__pdesc, __val)                        \
 164         SET_BITS_OFFSET_LE(__pdesc + 12, 28, 4, __val)
 165
 166 /* Dword 4 */
 167 #define SET_TX_DESC_RTS_RATE(__pdesc, __val)                    \
 168         SET_BITS_OFFSET_LE(__pdesc + 16, 0, 6, __val)
 169 #define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val)              \
 170         SET_BITS_OFFSET_LE(__pdesc + 16, 6, 1, __val)
 171 #define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val)           \
 172         SET_BITS_OFFSET_LE(__pdesc + 16, 7, 4, __val)
 173 #define SET_TX_DESC_CTS_ENABLE(__pdesc, __val)                  \
 174         SET_BITS_OFFSET_LE(__pdesc + 16, 11, 1, __val)
 175 #define SET_TX_DESC_RTS_ENABLE(__pdesc, __val)                  \
 176         SET_BITS_OFFSET_LE(__pdesc + 16, 12, 1, __val)
 177 #define SET_TX_DESC_RA_BRSR_ID(__pdesc, __val)                  \
 178         SET_BITS_OFFSET_LE(__pdesc + 16, 13, 3, __val)
 179 #define SET_TX_DESC_TXHT(__pdesc, __val)                        \
 180         SET_BITS_OFFSET_LE(__pdesc + 16, 16, 1, __val)
 181 #define SET_TX_DESC_TX_SHORT(__pdesc, __val)                    \
 182         SET_BITS_OFFSET_LE(__pdesc + 16, 17, 1, __val)
 183 #define SET_TX_DESC_TX_BANDWIDTH(__pdesc, __val)                \
 184         SET_BITS_OFFSET_LE(__pdesc + 16, 18, 1, __val)
 185 #define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val)              \
 186         SET_BITS_OFFSET_LE(__pdesc + 16, 19, 2, __val)
 187 #define SET_TX_DESC_TX_STBC(__pdesc, __val)                     \
 188         SET_BITS_OFFSET_LE(__pdesc + 16, 21, 2, __val)
 189 #define SET_TX_DESC_TX_REVERSE_DIRECTION(__pdesc, __val)        \
 190         SET_BITS_OFFSET_LE(__pdesc + 16, 23, 1, __val)
 191 #define SET_TX_DESC_RTS_HT(__pdesc, __val)                      \
 192         SET_BITS_OFFSET_LE(__pdesc + 16, 24, 1, __val)
 193 #define SET_TX_DESC_RTS_SHORT(__pdesc, __val)                   \
 194         SET_BITS_OFFSET_LE(__pdesc + 16, 25, 1, __val)
 195 #define SET_TX_DESC_RTS_BANDWIDTH(__pdesc, __val)               \
 196         SET_BITS_OFFSET_LE(__pdesc + 16, 26, 1, __val)
 197 #define SET_TX_DESC_RTS_SUB_CARRIER(__pdesc, __val)             \
 198         SET_BITS_OFFSET_LE(__pdesc + 16, 27, 2, __val)
 199 #define SET_TX_DESC_RTS_STBC(__pdesc, __val)                    \
 200         SET_BITS_OFFSET_LE(__pdesc + 16, 29, 2, __val)
 201 #define SET_TX_DESC_USER_RATE(__pdesc, __val)                   \
 202         SET_BITS_OFFSET_LE(__pdesc + 16, 31, 1, __val)
 203
 204 /* Dword 5 */
 205 #define SET_TX_DESC_PACKET_ID(__pdesc, __val)                   \
 206         SET_BITS_OFFSET_LE(__pdesc + 20, 0, 9, __val)
 207 #define SET_TX_DESC_TX_RATE(__pdesc, __val)                     \
 208         SET_BITS_OFFSET_LE(__pdesc + 20, 9, 6, __val)
 209 #define SET_TX_DESC_DISABLE_FB(__pdesc, __val)                  \
 210         SET_BITS_OFFSET_LE(__pdesc + 20, 15, 1, __val)
 211 #define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val)          \
 212         SET_BITS_OFFSET_LE(__pdesc + 20, 16, 5, __val)
 213 #define SET_TX_DESC_TX_AGC(__pdesc, __val)                      \
 214         SET_BITS_OFFSET_LE(__pdesc + 20, 21, 11, __val)
 215
 216 /* Dword 6 */
 217 #define SET_TX_DESC_IP_CHECK_SUM(__pdesc, __val)                \
 218         SET_BITS_OFFSET_LE(__pdesc + 24, 0, 16, __val)
 219 #define SET_TX_DESC_TCP_CHECK_SUM(__pdesc, __val)               \
 220         SET_BITS_OFFSET_LE(__pdesc + 24, 16, 16, __val)
 221
 222 /* Dword 7 */
 223 #define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val)              \
 224         SET_BITS_OFFSET_LE(__pdesc + 28, 0, 16, __val)
 225 #define SET_TX_DESC_IP_HEADER_OFFSET(__pdesc, __val)            \
 226         SET_BITS_OFFSET_LE(__pdesc + 28, 16, 8, __val)
 227 #define SET_TX_DESC_TCP_ENABLE(__pdesc, __val)                  \
 228         SET_BITS_OFFSET_LE(__pdesc + 28, 31, 1, __val)
 229
 230 /* Dword 8 */
 231 #define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val)           \
 232         SET_BITS_OFFSET_LE(__pdesc + 32, 0, 32, __val)
 233 #define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc)                  \
 234         SHIFT_AND_MASK_LE(__pdesc + 32, 0, 32)
 235
 236 /* Dword 9 */
 237 #define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val)           \
 238         SET_BITS_OFFSET_LE(__pdesc + 36, 0, 32, __val)
 239
 240 /* Because the PCI Tx descriptors are chaied at the
 241  * initialization and all the NextDescAddresses in
 242  * these descriptors cannot not be cleared (,or
 243  * driver/HW cannot find the next descriptor), the
 244  * offset 36 (NextDescAddresses) is reserved when
 245  * the desc is cleared. */
 246 #define TX_DESC_NEXT_DESC_OFFSET                        36
 247 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size)               \
 248         memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET))
 249
 250 /* Rx Desc */
 251 #define RX_STATUS_DESC_SIZE                             24
 252 #define RX_DRV_INFO_SIZE_UNIT                           8
 253
 254 /* DWORD 0 */
 255 #define SET_RX_STATUS_DESC_PKT_LEN(__pdesc, __val)              \
 256         SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
 257 #define SET_RX_STATUS_DESC_CRC32(__pdesc, __val)                \
 258         SET_BITS_OFFSET_LE(__pdesc, 14, 1, __val)
 259 #define SET_RX_STATUS_DESC_ICV(__pdesc, __val)                  \
 260         SET_BITS_OFFSET_LE(__pdesc, 15, 1, __val)
 261 #define SET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc, __val)         \
 262         SET_BITS_OFFSET_LE(__pdesc, 16, 4, __val)
 263 #define SET_RX_STATUS_DESC_SECURITY(__pdesc, __val)             \
 264         SET_BITS_OFFSET_LE(__pdesc, 20, 3, __val)
 265 #define SET_RX_STATUS_DESC_QOS(__pdesc, __val)                  \
 266         SET_BITS_OFFSET_LE(__pdesc, 23, 1, __val)
 267 #define SET_RX_STATUS_DESC_SHIFT(__pdesc, __val)                \
 268         SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val)
 269 #define SET_RX_STATUS_DESC_PHY_STATUS(__pdesc, __val)           \
 270         SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
 271 #define SET_RX_STATUS_DESC_SWDEC(__pdesc, __val)                \
 272         SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
 273 #define SET_RX_STATUS_DESC_LAST_SEG(__pdesc, __val)             \
 274         SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
 275 #define SET_RX_STATUS_DESC_FIRST_SEG(__pdesc, __val)            \
 276         SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
 277 #define SET_RX_STATUS_DESC_EOR(__pdesc, __val)                  \
 278         SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
 279 #define SET_RX_STATUS_DESC_OWN(__pdesc, __val)                  \
 280         SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
 281
 282 #define GET_RX_STATUS_DESC_PKT_LEN(__pdesc)                     \
 283         SHIFT_AND_MASK_LE(__pdesc, 0, 14)
 284 #define GET_RX_STATUS_DESC_CRC32(__pdesc)                       \
 285         SHIFT_AND_MASK_LE(__pdesc, 14, 1)
 286 #define GET_RX_STATUS_DESC_ICV(__pdesc)                         \
 287         SHIFT_AND_MASK_LE(__pdesc, 15, 1)
 288 #define GET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc)                \
 289         SHIFT_AND_MASK_LE(__pdesc, 16, 4)
 290 #define GET_RX_STATUS_DESC_SECURITY(__pdesc)                    \
 291         SHIFT_AND_MASK_LE(__pdesc, 20, 3)
 292 #define GET_RX_STATUS_DESC_QOS(__pdesc)                         \
 293         SHIFT_AND_MASK_LE(__pdesc, 23, 1)
 294 #define GET_RX_STATUS_DESC_SHIFT(__pdesc)                       \
 295         SHIFT_AND_MASK_LE(__pdesc, 24, 2)
 296 #define GET_RX_STATUS_DESC_PHY_STATUS(__pdesc)                  \
 297         SHIFT_AND_MASK_LE(__pdesc, 26, 1)
 298 #define GET_RX_STATUS_DESC_SWDEC(__pdesc)                       \
 299         SHIFT_AND_MASK_LE(__pdesc, 27, 1)
 300 #define GET_RX_STATUS_DESC_LAST_SEG(__pdesc)                    \
 301         SHIFT_AND_MASK_LE(__pdesc, 28, 1)
 302 #define GET_RX_STATUS_DESC_FIRST_SEG(__pdesc)                   \
 303         SHIFT_AND_MASK_LE(__pdesc, 29, 1)
 304 #define GET_RX_STATUS_DESC_EOR(__pdesc)                         \
 305         SHIFT_AND_MASK_LE(__pdesc, 30, 1)
 306 #define GET_RX_STATUS_DESC_OWN(__pdesc)                         \
 307         SHIFT_AND_MASK_LE(__pdesc, 31, 1)
 308
 309 /* DWORD 1 */
 310 #define SET_RX_STATUS_DESC_MACID(__pdesc, __val)                \
 311         SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val)
 312 #define SET_RX_STATUS_DESC_TID(__pdesc, __val)                  \
 313         SET_BITS_OFFSET_LE(__pdesc + 4, 5, 4, __val)
 314 #define SET_RX_STATUS_DESC_PAGGR(__pdesc, __val)                \
 315         SET_BITS_OFFSET_LE(__pdesc + 4, 14, 1, __val)
 316 #define SET_RX_STATUS_DESC_FAGGR(__pdesc, __val)                \
 317         SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val)
 318 #define SET_RX_STATUS_DESC_A1_FIT(__pdesc, __val)               \
 319         SET_BITS_OFFSET_LE(__pdesc + 4, 16, 4, __val)
 320 #define SET_RX_STATUS_DESC_A2_FIT(__pdesc, __val)               \
 321         SET_BITS_OFFSET_LE(__pdesc + 4, 20, 4, __val)
 322 #define SET_RX_STATUS_DESC_PAM(__pdesc, __val)                  \
 323         SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val)
 324 #define SET_RX_STATUS_DESC_PWR(__pdesc, __val)                  \
 325         SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val)
 326 #define SET_RX_STATUS_DESC_MOREDATA(__pdesc, __val)             \
 327         SET_BITS_OFFSET_LE(__pdesc + 4, 26, 1, __val)
 328 #define SET_RX_STATUS_DESC_MOREFRAG(__pdesc, __val)             \
 329         SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val)
 330 #define SET_RX_STATUS_DESC_TYPE(__pdesc, __val)                 \
 331         SET_BITS_OFFSET_LE(__pdesc + 4, 28, 2, __val)
 332 #define SET_RX_STATUS_DESC_MC(__pdesc, __val)                   \
 333         SET_BITS_OFFSET_LE(__pdesc + 4, 30, 1, __val)
 334 #define SET_RX_STATUS_DESC_BC(__pdesc, __val)                   \
 335         SET_BITS_OFFSET_LE(__pdesc + 4, 31, 1, __val)
 336
 337 #define GET_RX_STATUS_DEC_MACID(__pdesc)                        \
 338         SHIFT_AND_MASK_LE(__pdesc + 4, 0, 5)
 339 #define GET_RX_STATUS_DESC_TID(__pdesc)                         \
 340         SHIFT_AND_MASK_LE(__pdesc + 4, 5, 4)
 341 #define GET_RX_STATUS_DESC_PAGGR(__pdesc)                       \
 342         SHIFT_AND_MASK_LE(__pdesc + 4, 14, 1)
 343 #define GET_RX_STATUS_DESC_FAGGR(__pdesc)                       \
 344         SHIFT_AND_MASK_LE(__pdesc + 4, 15, 1)
 345 #define GET_RX_STATUS_DESC_A1_FIT(__pdesc)                      \
 346         SHIFT_AND_MASK_LE(__pdesc + 4, 16, 4)
 347 #define GET_RX_STATUS_DESC_A2_FIT(__pdesc)                      \
 348         SHIFT_AND_MASK_LE(__pdesc + 4, 20, 4)
 349 #define GET_RX_STATUS_DESC_PAM(__pdesc)                         \
 350         SHIFT_AND_MASK_LE(__pdesc + 4, 24, 1)
 351 #define GET_RX_STATUS_DESC_PWR(__pdesc)                         \
 352         SHIFT_AND_MASK_LE(__pdesc + 4, 25, 1)
 353 #define GET_RX_STATUS_DESC_MORE_DATA(__pdesc)                   \
 354         SHIFT_AND_MASK_LE(__pdesc + 4, 26, 1)
 355 #define GET_RX_STATUS_DESC_MORE_FRAG(__pdesc)                   \
 356         SHIFT_AND_MASK_LE(__pdesc + 4, 27, 1)
 357 #define GET_RX_STATUS_DESC_TYPE(__pdesc)                        \
 358         SHIFT_AND_MASK_LE(__pdesc + 4, 28, 2)
 359 #define GET_RX_STATUS_DESC_MC(__pdesc)                          \
 360         SHIFT_AND_MASK_LE(__pdesc + 4, 30, 1)
 361 #define GET_RX_STATUS_DESC_BC(__pdesc)                          \
 362         SHIFT_AND_MASK_LE(__pdesc + 4, 31, 1)
 363
 364 /* DWORD 2 */
 365 #define SET_RX_STATUS_DESC_SEQ(__pdesc, __val)                  \
 366         SET_BITS_OFFSET_LE(__pdesc + 8, 0, 12, __val)
 367 #define SET_RX_STATUS_DESC_FRAG(__pdesc, __val)                 \
 368         SET_BITS_OFFSET_LE(__pdesc + 8, 12, 4, __val)
 369 #define SET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc, __val)          \
 370         SET_BITS_OFFSET_LE(__pdesc + 8, 16, 8, __val)
 371 #define SET_RX_STATUS_DESC_NEXT_IND(__pdesc, __val)             \
 372         SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val)
 373
 374 #define GET_RX_STATUS_DESC_SEQ(__pdesc)                         \
 375         SHIFT_AND_MASK_LE(__pdesc + 8, 0, 12)
 376 #define GET_RX_STATUS_DESC_FRAG(__pdesc)                        \
 377         SHIFT_AND_MASK_LE(__pdesc + 8, 12, 4)
 378 #define GET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc)                 \
 379         SHIFT_AND_MASK_LE(__pdesc + 8, 16, 8)
 380 #define GET_RX_STATUS_DESC_NEXT_IND(__pdesc)                    \
 381         SHIFT_AND_MASK_LE(__pdesc + 8, 30, 1)
 382
 383 /* DWORD 3 */
 384 #define SET_RX_STATUS_DESC_RX_MCS(__pdesc, __val)               \
 385         SET_BITS_OFFSET_LE(__pdesc + 12, 0, 6, __val)
 386 #define SET_RX_STATUS_DESC_RX_HT(__pdesc, __val)                \
 387         SET_BITS_OFFSET_LE(__pdesc + 12, 6, 1, __val)
 388 #define SET_RX_STATUS_DESC_AMSDU(__pdesc, __val)                \
 389         SET_BITS_OFFSET_LE(__pdesc + 12, 7, 1, __val)
 390 #define SET_RX_STATUS_DESC_SPLCP(__pdesc, __val)                \
 391         SET_BITS_OFFSET_LE(__pdesc + 12, 8, 1, __val)
 392 #define SET_RX_STATUS_DESC_BW(__pdesc, __val)                   \
 393         SET_BITS_OFFSET_LE(__pdesc + 12, 9, 1, __val)
 394 #define SET_RX_STATUS_DESC_HTC(__pdesc, __val)                  \
 395         SET_BITS_OFFSET_LE(__pdesc + 12, 10, 1, __val)
 396 #define SET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc, __val)          \
 397         SET_BITS_OFFSET_LE(__pdesc + 12, 11, 1, __val)
 398 #define SET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc, __val)           \
 399         SET_BITS_OFFSET_LE(__pdesc + 12, 12, 1, __val)
 400 #define SET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc, __val)        \
 401         SET_BITS_OFFSET_LE(__pdesc + 12, 13, 1, __val)
 402 #define SET_RX_STATUS_DESC_HWPC_ERR(__pdesc, __val)             \
 403         SET_BITS_OFFSET_LE(__pdesc + 12, 14, 1, __val)
 404 #define SET_RX_STATUS_DESC_HWPC_IND(__pdesc, __val)             \
 405         SET_BITS_OFFSET_LE(__pdesc + 12, 15, 1, __val)
 406 #define SET_RX_STATUS_DESC_IV0(__pdesc, __val)                  \
 407         SET_BITS_OFFSET_LE(__pdesc + 12, 16, 16, __val)
 408
 409 #define GET_RX_STATUS_DESC_RX_MCS(__pdesc)                      \
 410         SHIFT_AND_MASK_LE(__pdesc + 12, 0, 6)
 411 #define GET_RX_STATUS_DESC_RX_HT(__pdesc)                       \
 412         SHIFT_AND_MASK_LE(__pdesc + 12, 6, 1)
 413 #define GET_RX_STATUS_DESC_AMSDU(__pdesc)                       \
 414         SHIFT_AND_MASK_LE(__pdesc + 12, 7, 1)
 415 #define GET_RX_STATUS_DESC_SPLCP(__pdesc)                       \
 416         SHIFT_AND_MASK_LE(__pdesc + 12, 8, 1)
 417 #define GET_RX_STATUS_DESC_BW(__pdesc)                          \
 418         SHIFT_AND_MASK_LE(__pdesc + 12, 9, 1)
 419 #define GET_RX_STATUS_DESC_HTC(__pdesc)                         \
 420         SHIFT_AND_MASK_LE(__pdesc + 12, 10, 1)
 421 #define GET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc)                 \
 422         SHIFT_AND_MASK_LE(__pdesc + 12, 11, 1)
 423 #define GET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc)                  \
 424         SHIFT_AND_MASK_LE(__pdesc + 12, 12, 1)
 425 #define GET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc)               \
 426         SHIFT_AND_MASK_LE(__pdesc + 12, 13, 1)
 427 #define GET_RX_STATUS_DESC_HWPC_ERR(__pdesc)                    \
 428         SHIFT_AND_MASK_LE(__pdesc + 12, 14, 1)
 429 #define GET_RX_STATUS_DESC_HWPC_IND(__pdesc)                    \
 430         SHIFT_AND_MASK_LE(__pdesc + 12, 15, 1)
 431 #define GET_RX_STATUS_DESC_IV0(__pdesc)                         \
 432         SHIFT_AND_MASK_LE(__pdesc + 12, 16, 16)
 433
 434 /* DWORD 4 */
 435 #define SET_RX_STATUS_DESC_IV1(__pdesc, __val)                  \
 436         SET_BITS_OFFSET_LE(__pdesc + 16, 0, 32, __val)
 437 #define GET_RX_STATUS_DESC_IV1(__pdesc)                         \
 438         SHIFT_AND_MASK_LE(__pdesc + 16, 0, 32)
 439
 440 /* DWORD 5 */
 441 #define SET_RX_STATUS_DESC_TSFL(__pdesc, __val)                 \
 442         SET_BITS_OFFSET_LE(__pdesc + 20, 0, 32, __val)
 443 #define GET_RX_STATUS_DESC_TSFL(__pdesc)                        \
 444         SHIFT_AND_MASK_LE(__pdesc + 20, 0, 32)
 445
 446 /* DWORD 6 */
 447 #define SET_RX_STATUS__DESC_BUFF_ADDR(__pdesc, __val)   \
 448         SET_BITS_OFFSET_LE(__pdesc + 24, 0, 32, __val)
 449 #define GET_RX_STATUS_DESC_BUFF_ADDR(__pdesc)                   \
 450         SHIFT_AND_MASK_LE(__pdesc + 24, 0, 32)
 451
 452 #define SE_RX_HAL_IS_CCK_RATE(_pdesc)\
 453         (GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE1M ||    \
 454          GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE2M ||    \
 455          GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE5_5M ||\
 456          GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE11M)
 457
 458 enum rf_optype {
 459         RF_OP_BY_SW_3WIRE = 0,
 460         RF_OP_BY_FW,
 461         RF_OP_MAX
 462 };
 463
 464 enum ic_inferiority {
 465         IC_INFERIORITY_A = 0,
 466         IC_INFERIORITY_B = 1,
 467 };
 468
 469 enum fwcmd_iotype {
 470         /* For DIG DM */
 471         FW_CMD_DIG_ENABLE = 0,
 472         FW_CMD_DIG_DISABLE = 1,
 473         FW_CMD_DIG_HALT = 2,
 474         FW_CMD_DIG_RESUME = 3,
 475         /* For High Power DM */
 476         FW_CMD_HIGH_PWR_ENABLE = 4,
 477         FW_CMD_HIGH_PWR_DISABLE = 5,
 478         /* For Rate adaptive DM */
 479         FW_CMD_RA_RESET = 6,
 480         FW_CMD_RA_ACTIVE = 7,
 481         FW_CMD_RA_REFRESH_N = 8,
 482         FW_CMD_RA_REFRESH_BG = 9,
 483         FW_CMD_RA_INIT = 10,
 484         /* For FW supported IQK */
 485         FW_CMD_IQK_INIT = 11,
 486         /* Tx power tracking switch,
 487          * MP driver only */
 488         FW_CMD_TXPWR_TRACK_ENABLE = 12,
 489         /* Tx power tracking switch,
 490          * MP driver only */
 491         FW_CMD_TXPWR_TRACK_DISABLE = 13,
 492         /* Tx power tracking with thermal
 493          * indication, for Normal driver */
 494         FW_CMD_TXPWR_TRACK_THERMAL = 14,
 495         FW_CMD_PAUSE_DM_BY_SCAN = 15,
 496         FW_CMD_RESUME_DM_BY_SCAN = 16,
 497         FW_CMD_RA_REFRESH_N_COMB = 17,
 498         FW_CMD_RA_REFRESH_BG_COMB = 18,
 499         FW_CMD_ANTENNA_SW_ENABLE = 19,
 500         FW_CMD_ANTENNA_SW_DISABLE = 20,
 501         /* Tx Status report for CCX from FW */
 502         FW_CMD_TX_FEEDBACK_CCX_ENABLE = 21,
 503         /* Indifate firmware that driver
 504          * enters LPS, For PS-Poll issue */
 505         FW_CMD_LPS_ENTER = 22,
 506         /* Indicate firmware that driver
 507          * leave LPS*/
 508         FW_CMD_LPS_LEAVE = 23,
 509         /* Set DIG mode to signal strength */
 510         FW_CMD_DIG_MODE_SS = 24,
 511         /* Set DIG mode to false alarm. */
 512         FW_CMD_DIG_MODE_FA = 25,
 513         FW_CMD_ADD_A2_ENTRY = 26,
 514         FW_CMD_CTRL_DM_BY_DRIVER = 27,
 515         FW_CMD_CTRL_DM_BY_DRIVER_NEW = 28,
 516         FW_CMD_PAPE_CONTROL = 29,
 517         FW_CMD_IQK_ENABLE = 30,
 518 };
 519
 520 /* Driver info contain PHY status
 521  * and other variabel size info
 522  * PHY Status content as below
 523  */
 524 struct  rx_fwinfo {
 525         /* DWORD 0 */
 526         u8 gain_trsw[4];
 527         /* DWORD 1 */
 528         u8 pwdb_all;
 529         u8 cfosho[4];
 530         /* DWORD 2 */
 531         u8 cfotail[4];
 532         /* DWORD 3 */
 533         s8 rxevm[2];
 534         s8 rxsnr[4];
 535         /* DWORD 4 */
 536         u8 pdsnr[2];
 537         /* DWORD 5 */
 538         u8 csi_current[2];
 539         u8 csi_target[2];
 540         /* DWORD 6 */
 541         u8 sigevm;
 542         u8 max_ex_pwr;
 543         u8 ex_intf_flag:1;
 544         u8 sgi_en:1;
 545         u8 rxsc:2;
 546         u8 reserve:4;
 547 };
 548
 549 struct phy_sts_cck_8192s_t {
 550         u8 adc_pwdb_x[4];
 551         u8 sq_rpt;
 552         u8 cck_agc_rpt;
 553 };
 554
 555 #endif
 556