drivers/char/hw_random/xgene-rng.c

   1 /*
   2  * APM X-Gene SoC RNG Driver
   3  *
   4  * Copyright (c) 2014, Applied Micro Circuits Corporation
   5  * Author: Rameshwar Prasad Sahu <rsahu@apm.com>
   6  *         Shamal Winchurkar <swinchurkar@apm.com>
   7  *         Feng Kan <fkan@apm.com>
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  *
  22  */
  23
  24 #include <linux/acpi.h>
  25 #include <linux/clk.h>
  26 #include <linux/delay.h>
  27 #include <linux/hw_random.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/module.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/of_address.h>
  34 #include <linux/timer.h>
  35
  36 #define RNG_MAX_DATUM                   4
  37 #define MAX_TRY                         100
  38 #define XGENE_RNG_RETRY_COUNT           20
  39 #define XGENE_RNG_RETRY_INTERVAL        10
  40
  41 /* RNG  Registers */
  42 #define RNG_INOUT_0                     0x00
  43 #define RNG_INTR_STS_ACK                0x10
  44 #define RNG_CONTROL                     0x14
  45 #define RNG_CONFIG                      0x18
  46 #define RNG_ALARMCNT                    0x1c
  47 #define RNG_FROENABLE                   0x20
  48 #define RNG_FRODETUNE                   0x24
  49 #define RNG_ALARMMASK                   0x28
  50 #define RNG_ALARMSTOP                   0x2c
  51 #define RNG_OPTIONS                     0x78
  52 #define RNG_EIP_REV                     0x7c
  53
  54 #define MONOBIT_FAIL_MASK               BIT(7)
  55 #define POKER_FAIL_MASK                 BIT(6)
  56 #define LONG_RUN_FAIL_MASK              BIT(5)
  57 #define RUN_FAIL_MASK                   BIT(4)
  58 #define NOISE_FAIL_MASK                 BIT(3)
  59 #define STUCK_OUT_MASK                  BIT(2)
  60 #define SHUTDOWN_OFLO_MASK              BIT(1)
  61 #define READY_MASK                      BIT(0)
  62
  63 #define MAJOR_HW_REV_RD(src)            (((src) & 0x0f000000) >> 24)
  64 #define MINOR_HW_REV_RD(src)            (((src) & 0x00f00000) >> 20)
  65 #define HW_PATCH_LEVEL_RD(src)          (((src) & 0x000f0000) >> 16)
  66 #define MAX_REFILL_CYCLES_SET(dst, src) \
  67                         ((dst & ~0xffff0000) | (((u32)src << 16) & 0xffff0000))
  68 #define MIN_REFILL_CYCLES_SET(dst, src) \
  69                         ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
  70 #define ALARM_THRESHOLD_SET(dst, src) \
  71                         ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
  72 #define ENABLE_RNG_SET(dst, src) \
  73                         ((dst & ~BIT(10)) | (((u32)src << 10) & BIT(10)))
  74 #define REGSPEC_TEST_MODE_SET(dst, src) \
  75                         ((dst & ~BIT(8)) | (((u32)src << 8) & BIT(8)))
  76 #define MONOBIT_FAIL_MASK_SET(dst, src) \
  77                         ((dst & ~BIT(7)) | (((u32)src << 7) & BIT(7)))
  78 #define POKER_FAIL_MASK_SET(dst, src) \
  79                         ((dst & ~BIT(6)) | (((u32)src << 6) & BIT(6)))
  80 #define LONG_RUN_FAIL_MASK_SET(dst, src) \
  81                         ((dst & ~BIT(5)) | (((u32)src << 5) & BIT(5)))
  82 #define RUN_FAIL_MASK_SET(dst, src) \
  83                         ((dst & ~BIT(4)) | (((u32)src << 4) & BIT(4)))
  84 #define NOISE_FAIL_MASK_SET(dst, src) \
  85                         ((dst & ~BIT(3)) | (((u32)src << 3) & BIT(3)))
  86 #define STUCK_OUT_MASK_SET(dst, src) \
  87                         ((dst & ~BIT(2)) | (((u32)src << 2) & BIT(2)))
  88 #define SHUTDOWN_OFLO_MASK_SET(dst, src) \
  89                         ((dst & ~BIT(1)) | (((u32)src << 1) & BIT(1)))
  90
  91 struct xgene_rng_dev {
  92         u32 irq;
  93         void  __iomem *csr_base;
  94         u32 revision;
  95         u32 datum_size;
  96         u32 failure_cnt;        /* Failure count last minute */
  97         unsigned long failure_ts;/* First failure timestamp */
  98         struct timer_list failure_timer;
  99         struct device *dev;
 100         struct clk *clk;
 101 };
 102
 103 static void xgene_rng_expired_timer(struct timer_list *t)
 104 {
 105         struct xgene_rng_dev *ctx = from_timer(ctx, t, failure_timer);
 106
 107         /* Clear failure counter as timer expired */
 108         disable_irq(ctx->irq);
 109         ctx->failure_cnt = 0;
 110         del_timer(&ctx->failure_timer);
 111         enable_irq(ctx->irq);
 112 }
 113
 114 static void xgene_rng_start_timer(struct xgene_rng_dev *ctx)
 115 {
 116         ctx->failure_timer.expires = jiffies + 120 * HZ;
 117         add_timer(&ctx->failure_timer);
 118 }
 119
 120 /*
 121  * Initialize or reinit free running oscillators (FROs)
 122  */
 123 static void xgene_rng_init_fro(struct xgene_rng_dev *ctx, u32 fro_val)
 124 {
 125         writel(fro_val, ctx->csr_base + RNG_FRODETUNE);
 126         writel(0x00000000, ctx->csr_base + RNG_ALARMMASK);
 127         writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP);
 128         writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE);
 129 }
 130
 131 static void xgene_rng_chk_overflow(struct xgene_rng_dev *ctx)
 132 {
 133         u32 val;
 134
 135         val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
 136         if (val & MONOBIT_FAIL_MASK)
 137                 /*
 138                  * LFSR detected an out-of-bounds number of 1s after
 139                  * checking 20,000 bits (test T1 as specified in the
 140                  * AIS-31 standard)
 141                  */
 142                 dev_err(ctx->dev, "test monobit failure error 0x%08X\n", val);
 143         if (val & POKER_FAIL_MASK)
 144                 /*
 145                  * LFSR detected an out-of-bounds value in at least one
 146                  * of the 16 poker_count_X counters or an out of bounds sum
 147                  * of squares value after checking 20,000 bits (test T2 as
 148                  * specified in the AIS-31 standard)
 149                  */
 150                 dev_err(ctx->dev, "test poker failure error 0x%08X\n", val);
 151         if (val & LONG_RUN_FAIL_MASK)
 152                 /*
 153                  * LFSR detected a sequence of 34 identical bits
 154                  * (test T4 as specified in the AIS-31 standard)
 155                  */
 156                 dev_err(ctx->dev, "test long run failure error 0x%08X\n", val);
 157         if (val & RUN_FAIL_MASK)
 158                 /*
 159                  * LFSR detected an outof-bounds value for at least one
 160                  * of the running counters after checking 20,000 bits
 161                  * (test T3 as specified in the AIS-31 standard)
 162                  */
 163                 dev_err(ctx->dev, "test run failure error 0x%08X\n", val);
 164         if (val & NOISE_FAIL_MASK)
 165                 /* LFSR detected a sequence of 48 identical bits */
 166                 dev_err(ctx->dev, "noise failure error 0x%08X\n", val);
 167         if (val & STUCK_OUT_MASK)
 168                 /*
 169                  * Detected output data registers generated same value twice
 170                  * in a row
 171                  */
 172                 dev_err(ctx->dev, "stuck out failure error 0x%08X\n", val);
 173
 174         if (val & SHUTDOWN_OFLO_MASK) {
 175                 u32 frostopped;
 176
 177                 /* FROs shut down after a second error event. Try recover. */
 178                 if (++ctx->failure_cnt == 1) {
 179                         /* 1st time, just recover */
 180                         ctx->failure_ts = jiffies;
 181                         frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
 182                         xgene_rng_init_fro(ctx, frostopped);
 183
 184                         /*
 185                          * We must start a timer to clear out this error
 186                          * in case the system timer wrap around
 187                          */
 188                         xgene_rng_start_timer(ctx);
 189                 } else {
 190                         /* 2nd time failure in lesser than 1 minute? */
 191                         if (time_after(ctx->failure_ts + 60 * HZ, jiffies)) {
 192                                 dev_err(ctx->dev,
 193                                         "FRO shutdown failure error 0x%08X\n",
 194                                         val);
 195                         } else {
 196                                 /* 2nd time failure after 1 minutes, recover */
 197                                 ctx->failure_ts = jiffies;
 198                                 ctx->failure_cnt = 1;
 199                                 /*
 200                                  * We must start a timer to clear out this
 201                                  * error in case the system timer wrap
 202                                  * around
 203                                  */
 204                                 xgene_rng_start_timer(ctx);
 205                         }
 206                         frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
 207                         xgene_rng_init_fro(ctx, frostopped);
 208                 }
 209         }
 210         /* Clear them all */
 211         writel(val, ctx->csr_base + RNG_INTR_STS_ACK);
 212 }
 213
 214 static irqreturn_t xgene_rng_irq_handler(int irq, void *id)
 215 {
 216         struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) id;
 217
 218         /* RNG Alarm Counter overflow */
 219         xgene_rng_chk_overflow(ctx);
 220
 221         return IRQ_HANDLED;
 222 }
 223
 224 static int xgene_rng_data_present(struct hwrng *rng, int wait)
 225 {
 226         struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
 227         u32 i, val = 0;
 228
 229         for (i = 0; i < XGENE_RNG_RETRY_COUNT; i++) {
 230                 val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
 231                 if ((val & READY_MASK) || !wait)
 232                         break;
 233                 udelay(XGENE_RNG_RETRY_INTERVAL);
 234         }
 235
 236         return (val & READY_MASK);
 237 }
 238
 239 static int xgene_rng_data_read(struct hwrng *rng, u32 *data)
 240 {
 241         struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
 242         int i;
 243
 244         for (i = 0; i < ctx->datum_size; i++)
 245                 data[i] = readl(ctx->csr_base + RNG_INOUT_0 + i * 4);
 246
 247         /* Clear ready bit to start next transaction */
 248         writel(READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
 249
 250         return ctx->datum_size << 2;
 251 }
 252
 253 static void xgene_rng_init_internal(struct xgene_rng_dev *ctx)
 254 {
 255         u32 val;
 256
 257         writel(0x00000000, ctx->csr_base + RNG_CONTROL);
 258
 259         val = MAX_REFILL_CYCLES_SET(0, 10);
 260         val = MIN_REFILL_CYCLES_SET(val, 10);
 261         writel(val, ctx->csr_base + RNG_CONFIG);
 262
 263         val = ALARM_THRESHOLD_SET(0, 0xFF);
 264         writel(val, ctx->csr_base + RNG_ALARMCNT);
 265
 266         xgene_rng_init_fro(ctx, 0);
 267
 268         writel(MONOBIT_FAIL_MASK |
 269                 POKER_FAIL_MASK |
 270                 LONG_RUN_FAIL_MASK |
 271                 RUN_FAIL_MASK |
 272                 NOISE_FAIL_MASK |
 273                 STUCK_OUT_MASK |
 274                 SHUTDOWN_OFLO_MASK |
 275                 READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
 276
 277         val = ENABLE_RNG_SET(0, 1);
 278         val = MONOBIT_FAIL_MASK_SET(val, 1);
 279         val = POKER_FAIL_MASK_SET(val, 1);
 280         val = LONG_RUN_FAIL_MASK_SET(val, 1);
 281         val = RUN_FAIL_MASK_SET(val, 1);
 282         val = NOISE_FAIL_MASK_SET(val, 1);
 283         val = STUCK_OUT_MASK_SET(val, 1);
 284         val = SHUTDOWN_OFLO_MASK_SET(val, 1);
 285         writel(val, ctx->csr_base + RNG_CONTROL);
 286 }
 287
 288 static int xgene_rng_init(struct hwrng *rng)
 289 {
 290         struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
 291
 292         ctx->failure_cnt = 0;
 293         timer_setup(&ctx->failure_timer, xgene_rng_expired_timer, 0);
 294
 295         ctx->revision = readl(ctx->csr_base + RNG_EIP_REV);
 296
 297         dev_dbg(ctx->dev, "Rev %d.%d.%d\n",
 298                 MAJOR_HW_REV_RD(ctx->revision),
 299                 MINOR_HW_REV_RD(ctx->revision),
 300                 HW_PATCH_LEVEL_RD(ctx->revision));
 301
 302         dev_dbg(ctx->dev, "Options 0x%08X",
 303                 readl(ctx->csr_base + RNG_OPTIONS));
 304
 305         xgene_rng_init_internal(ctx);
 306
 307         ctx->datum_size = RNG_MAX_DATUM;
 308
 309         return 0;
 310 }
 311
 312 #ifdef CONFIG_ACPI
 313 static const struct acpi_device_id xgene_rng_acpi_match[] = {
 314         { "APMC0D18", },
 315         { }
 316 };
 317 MODULE_DEVICE_TABLE(acpi, xgene_rng_acpi_match);
 318 #endif
 319
 320 static struct hwrng xgene_rng_func = {
 321         .name           = "xgene-rng",
 322         .init           = xgene_rng_init,
 323         .data_present   = xgene_rng_data_present,
 324         .data_read      = xgene_rng_data_read,
 325 };
 326
 327 static int xgene_rng_probe(struct platform_device *pdev)
 328 {
 329         struct resource *res;
 330         struct xgene_rng_dev *ctx;
 331         int rc = 0;
 332
 333         ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
 334         if (!ctx)
 335                 return -ENOMEM;
 336
 337         ctx->dev = &pdev->dev;
 338         platform_set_drvdata(pdev, ctx);
 339
 340         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 341         ctx->csr_base = devm_ioremap_resource(&pdev->dev, res);
 342         if (IS_ERR(ctx->csr_base))
 343                 return PTR_ERR(ctx->csr_base);
 344
 345         rc = platform_get_irq(pdev, 0);
 346         if (rc < 0) {
 347                 dev_err(&pdev->dev, "No IRQ resource\n");
 348                 return rc;
 349         }
 350         ctx->irq = rc;
 351
 352         dev_dbg(&pdev->dev, "APM X-Gene RNG BASE %p ALARM IRQ %d",
 353                 ctx->csr_base, ctx->irq);
 354
 355         rc = devm_request_irq(&pdev->dev, ctx->irq, xgene_rng_irq_handler, 0,
 356                                 dev_name(&pdev->dev), ctx);
 357         if (rc) {
 358                 dev_err(&pdev->dev, "Could not request RNG alarm IRQ\n");
 359                 return rc;
 360         }
 361
 362         /* Enable IP clock */
 363         ctx->clk = devm_clk_get(&pdev->dev, NULL);
 364         if (IS_ERR(ctx->clk)) {
 365                 dev_warn(&pdev->dev, "Couldn't get the clock for RNG\n");
 366         } else {
 367                 rc = clk_prepare_enable(ctx->clk);
 368                 if (rc) {
 369                         dev_warn(&pdev->dev,
 370                                  "clock prepare enable failed for RNG");
 371                         return rc;
 372                 }
 373         }
 374
 375         xgene_rng_func.priv = (unsigned long) ctx;
 376
 377         rc = hwrng_register(&xgene_rng_func);
 378         if (rc) {
 379                 dev_err(&pdev->dev, "RNG registering failed error %d\n", rc);
 380                 if (!IS_ERR(ctx->clk))
 381                         clk_disable_unprepare(ctx->clk);
 382                 return rc;
 383         }
 384
 385         rc = device_init_wakeup(&pdev->dev, 1);
 386         if (rc) {
 387                 dev_err(&pdev->dev, "RNG device_init_wakeup failed error %d\n",
 388                         rc);
 389                 if (!IS_ERR(ctx->clk))
 390                         clk_disable_unprepare(ctx->clk);
 391                 hwrng_unregister(&xgene_rng_func);
 392                 return rc;
 393         }
 394
 395         return 0;
 396 }
 397
 398 static int xgene_rng_remove(struct platform_device *pdev)
 399 {
 400         struct xgene_rng_dev *ctx = platform_get_drvdata(pdev);
 401         int rc;
 402
 403         rc = device_init_wakeup(&pdev->dev, 0);
 404         if (rc)
 405                 dev_err(&pdev->dev, "RNG init wakeup failed error %d\n", rc);
 406         if (!IS_ERR(ctx->clk))
 407                 clk_disable_unprepare(ctx->clk);
 408         hwrng_unregister(&xgene_rng_func);
 409
 410         return rc;
 411 }
 412
 413 static const struct of_device_id xgene_rng_of_match[] = {
 414         { .compatible = "apm,xgene-rng" },
 415         { }
 416 };
 417
 418 MODULE_DEVICE_TABLE(of, xgene_rng_of_match);
 419
 420 static struct platform_driver xgene_rng_driver = {
 421         .probe = xgene_rng_probe,
 422         .remove = xgene_rng_remove,
 423         .driver = {
 424                 .name           = "xgene-rng",
 425                 .of_match_table = xgene_rng_of_match,
 426                 .acpi_match_table = ACPI_PTR(xgene_rng_acpi_match),
 427         },
 428 };
 429
 430 module_platform_driver(xgene_rng_driver);
 431 MODULE_DESCRIPTION("APM X-Gene RNG driver");
 432 MODULE_LICENSE("GPL");