drivers/phy/st/phy-stm32-usbphyc.c

   1 // SPDX-Licence-Identifier: GPL-2.0
   2 /*
   3  * STMicroelectronics STM32 USB PHY Controller driver
   4  *
   5  * Copyright (C) 2018 STMicroelectronics
   6  * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
   7  */
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/io.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/reset.h>
  17
  18 #define STM32_USBPHYC_PLL       0x0
  19 #define STM32_USBPHYC_MISC      0x8
  20 #define STM32_USBPHYC_VERSION   0x3F4
  21
  22 /* STM32_USBPHYC_PLL bit fields */
  23 #define PLLNDIV                 GENMASK(6, 0)
  24 #define PLLFRACIN               GENMASK(25, 10)
  25 #define PLLEN                   BIT(26)
  26 #define PLLSTRB                 BIT(27)
  27 #define PLLSTRBYP               BIT(28)
  28 #define PLLFRACCTL              BIT(29)
  29 #define PLLDITHEN0              BIT(30)
  30 #define PLLDITHEN1              BIT(31)
  31
  32 /* STM32_USBPHYC_MISC bit fields */
  33 #define SWITHOST                BIT(0)
  34
  35 /* STM32_USBPHYC_VERSION bit fields */
  36 #define MINREV                  GENMASK(3, 0)
  37 #define MAJREV                  GENMASK(7, 4)
  38
  39 static const char * const supplies_names[] = {
  40         "vdda1v1",      /* 1V1 */
  41         "vdda1v8",      /* 1V8 */
  42 };
  43
  44 #define NUM_SUPPLIES            ARRAY_SIZE(supplies_names)
  45
  46 #define PLL_LOCK_TIME_US        100
  47 #define PLL_PWR_DOWN_TIME_US    5
  48 #define PLL_FVCO_MHZ            2880
  49 #define PLL_INFF_MIN_RATE_HZ    19200000
  50 #define PLL_INFF_MAX_RATE_HZ    38400000
  51 #define HZ_PER_MHZ              1000000L
  52
  53 struct pll_params {
  54         u8 ndiv;
  55         u16 frac;
  56 };
  57
  58 struct stm32_usbphyc_phy {
  59         struct phy *phy;
  60         struct stm32_usbphyc *usbphyc;
  61         struct regulator_bulk_data supplies[NUM_SUPPLIES];
  62         u32 index;
  63         bool active;
  64 };
  65
  66 struct stm32_usbphyc {
  67         struct device *dev;
  68         void __iomem *base;
  69         struct clk *clk;
  70         struct reset_control *rst;
  71         struct stm32_usbphyc_phy **phys;
  72         int nphys;
  73         int switch_setup;
  74 };
  75
  76 static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
  77 {
  78         writel_relaxed(readl_relaxed(reg) | bits, reg);
  79 }
  80
  81 static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
  82 {
  83         writel_relaxed(readl_relaxed(reg) & ~bits, reg);
  84 }
  85
  86 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
  87                                          struct pll_params *pll_params)
  88 {
  89         unsigned long long fvco, ndiv, frac;
  90
  91         /*    _
  92          *   | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
  93          *   | FVCO = 2880MHz
  94          *  <
  95          *   | NDIV = integer part of input bits to set the LDF
  96          *   |_FRACT = fractional part of input bits to set the LDF
  97          *  =>  PLLNDIV = integer part of (FVCO / (INFF*2))
  98          *  =>  PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
  99          * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
 100          */
 101         fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
 102
 103         ndiv = fvco;
 104         do_div(ndiv, (clk_rate * 2));
 105         pll_params->ndiv = (u8)ndiv;
 106
 107         frac = fvco * (1 << 16);
 108         do_div(frac, (clk_rate * 2));
 109         frac = frac - (ndiv * (1 << 16));
 110         pll_params->frac = (u16)frac;
 111 }
 112
 113 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
 114 {
 115         struct pll_params pll_params;
 116         u32 clk_rate = clk_get_rate(usbphyc->clk);
 117         u32 ndiv, frac;
 118         u32 usbphyc_pll;
 119
 120         if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
 121             (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
 122                 dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
 123                         clk_rate);
 124                 return -EINVAL;
 125         }
 126
 127         stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
 128         ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
 129         frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
 130
 131         usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
 132
 133         if (pll_params.frac)
 134                 usbphyc_pll |= PLLFRACCTL | frac;
 135
 136         writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
 137
 138         dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
 139                 clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
 140                 FIELD_GET(PLLFRACIN, usbphyc_pll));
 141
 142         return 0;
 143 }
 144
 145 static bool stm32_usbphyc_has_one_phy_active(struct stm32_usbphyc *usbphyc)
 146 {
 147         int i;
 148
 149         for (i = 0; i < usbphyc->nphys; i++)
 150                 if (usbphyc->phys[i]->active)
 151                         return true;
 152
 153         return false;
 154 }
 155
 156 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
 157 {
 158         void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
 159         bool pllen = (readl_relaxed(pll_reg) & PLLEN);
 160         int ret;
 161
 162         /* Check if one phy port has already configured the pll */
 163         if (pllen && stm32_usbphyc_has_one_phy_active(usbphyc))
 164                 return 0;
 165
 166         if (pllen) {
 167                 stm32_usbphyc_clr_bits(pll_reg, PLLEN);
 168                 /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
 169                 udelay(PLL_PWR_DOWN_TIME_US);
 170         }
 171
 172         ret = stm32_usbphyc_pll_init(usbphyc);
 173         if (ret)
 174                 return ret;
 175
 176         stm32_usbphyc_set_bits(pll_reg, PLLEN);
 177
 178         /* Wait for maximum lock time */
 179         udelay(PLL_LOCK_TIME_US);
 180
 181         if (!(readl_relaxed(pll_reg) & PLLEN)) {
 182                 dev_err(usbphyc->dev, "PLLEN not set\n");
 183                 return -EIO;
 184         }
 185
 186         return 0;
 187 }
 188
 189 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
 190 {
 191         void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
 192
 193         /* Check if other phy port active */
 194         if (stm32_usbphyc_has_one_phy_active(usbphyc))
 195                 return 0;
 196
 197         stm32_usbphyc_clr_bits(pll_reg, PLLEN);
 198         /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
 199         udelay(PLL_PWR_DOWN_TIME_US);
 200
 201         if (readl_relaxed(pll_reg) & PLLEN) {
 202                 dev_err(usbphyc->dev, "PLL not reset\n");
 203                 return -EIO;
 204         }
 205
 206         return 0;
 207 }
 208
 209 static int stm32_usbphyc_phy_init(struct phy *phy)
 210 {
 211         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 212         struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
 213         int ret;
 214
 215         ret = stm32_usbphyc_pll_enable(usbphyc);
 216         if (ret)
 217                 return ret;
 218
 219         usbphyc_phy->active = true;
 220
 221         return 0;
 222 }
 223
 224 static int stm32_usbphyc_phy_exit(struct phy *phy)
 225 {
 226         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 227         struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
 228
 229         usbphyc_phy->active = false;
 230
 231         return stm32_usbphyc_pll_disable(usbphyc);
 232 }
 233
 234 static int stm32_usbphyc_phy_power_on(struct phy *phy)
 235 {
 236         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 237
 238         return regulator_bulk_enable(NUM_SUPPLIES, usbphyc_phy->supplies);
 239 }
 240
 241 static int stm32_usbphyc_phy_power_off(struct phy *phy)
 242 {
 243         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 244
 245         return regulator_bulk_disable(NUM_SUPPLIES, usbphyc_phy->supplies);
 246 }
 247
 248 static const struct phy_ops stm32_usbphyc_phy_ops = {
 249         .init = stm32_usbphyc_phy_init,
 250         .exit = stm32_usbphyc_phy_exit,
 251         .power_on = stm32_usbphyc_phy_power_on,
 252         .power_off = stm32_usbphyc_phy_power_off,
 253         .owner = THIS_MODULE,
 254 };
 255
 256 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
 257                                        u32 utmi_switch)
 258 {
 259         if (!utmi_switch)
 260                 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
 261                                        SWITHOST);
 262         else
 263                 stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
 264                                        SWITHOST);
 265         usbphyc->switch_setup = utmi_switch;
 266 }
 267
 268 static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
 269                                           struct of_phandle_args *args)
 270 {
 271         struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
 272         struct stm32_usbphyc_phy *usbphyc_phy = NULL;
 273         struct device_node *phynode = args->np;
 274         int port = 0;
 275
 276         for (port = 0; port < usbphyc->nphys; port++) {
 277                 if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
 278                         usbphyc_phy = usbphyc->phys[port];
 279                         break;
 280                 }
 281         }
 282         if (!usbphyc_phy) {
 283                 dev_err(dev, "failed to find phy\n");
 284                 return ERR_PTR(-EINVAL);
 285         }
 286
 287         if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
 288             ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
 289                 dev_err(dev, "invalid number of cells for phy port%d\n",
 290                         usbphyc_phy->index);
 291                 return ERR_PTR(-EINVAL);
 292         }
 293
 294         /* Configure the UTMI switch for PHY port#2 */
 295         if (usbphyc_phy->index == 1) {
 296                 if (usbphyc->switch_setup < 0) {
 297                         stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
 298                 } else {
 299                         if (args->args[0] != usbphyc->switch_setup) {
 300                                 dev_err(dev, "phy port1 already used\n");
 301                                 return ERR_PTR(-EBUSY);
 302                         }
 303                 }
 304         }
 305
 306         return usbphyc_phy->phy;
 307 }
 308
 309 static int stm32_usbphyc_probe(struct platform_device *pdev)
 310 {
 311         struct stm32_usbphyc *usbphyc;
 312         struct device *dev = &pdev->dev;
 313         struct device_node *child, *np = dev->of_node;
 314         struct resource *res;
 315         struct phy_provider *phy_provider;
 316         u32 version;
 317         int ret, port = 0;
 318
 319         usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
 320         if (!usbphyc)
 321                 return -ENOMEM;
 322         usbphyc->dev = dev;
 323         dev_set_drvdata(dev, usbphyc);
 324
 325         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 326         usbphyc->base = devm_ioremap_resource(dev, res);
 327         if (IS_ERR(usbphyc->base))
 328                 return PTR_ERR(usbphyc->base);
 329
 330         usbphyc->clk = devm_clk_get(dev, 0);
 331         if (IS_ERR(usbphyc->clk)) {
 332                 ret = PTR_ERR(usbphyc->clk);
 333                 dev_err(dev, "clk get failed: %d\n", ret);
 334                 return ret;
 335         }
 336
 337         ret = clk_prepare_enable(usbphyc->clk);
 338         if (ret) {
 339                 dev_err(dev, "clk enable failed: %d\n", ret);
 340                 return ret;
 341         }
 342
 343         usbphyc->rst = devm_reset_control_get(dev, 0);
 344         if (!IS_ERR(usbphyc->rst)) {
 345                 reset_control_assert(usbphyc->rst);
 346                 udelay(2);
 347                 reset_control_deassert(usbphyc->rst);
 348         }
 349
 350         usbphyc->switch_setup = -EINVAL;
 351         usbphyc->nphys = of_get_child_count(np);
 352         usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
 353                                      sizeof(*usbphyc->phys), GFP_KERNEL);
 354         if (!usbphyc->phys) {
 355                 ret = -ENOMEM;
 356                 goto clk_disable;
 357         }
 358
 359         for_each_child_of_node(np, child) {
 360                 struct stm32_usbphyc_phy *usbphyc_phy;
 361                 struct phy *phy;
 362                 u32 index;
 363                 int i;
 364
 365                 phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
 366                 if (IS_ERR(phy)) {
 367                         ret = PTR_ERR(phy);
 368                         if (ret != -EPROBE_DEFER)
 369                                 dev_err(dev, "failed to create phy%d: %d\n",
 370                                         port, ret);
 371                         goto put_child;
 372                 }
 373
 374                 usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
 375                                            GFP_KERNEL);
 376                 if (!usbphyc_phy) {
 377                         ret = -ENOMEM;
 378                         goto put_child;
 379                 }
 380
 381                 for (i = 0; i < NUM_SUPPLIES; i++)
 382                         usbphyc_phy->supplies[i].supply = supplies_names[i];
 383
 384                 ret = devm_regulator_bulk_get(&phy->dev, NUM_SUPPLIES,
 385                                               usbphyc_phy->supplies);
 386                 if (ret) {
 387                         if (ret != -EPROBE_DEFER)
 388                                 dev_err(&phy->dev,
 389                                         "failed to get regulators: %d\n", ret);
 390                         goto put_child;
 391                 }
 392
 393                 ret = of_property_read_u32(child, "reg", &index);
 394                 if (ret || index > usbphyc->nphys) {
 395                         dev_err(&phy->dev, "invalid reg property: %d\n", ret);
 396                         goto put_child;
 397                 }
 398
 399                 usbphyc->phys[port] = usbphyc_phy;
 400                 phy_set_bus_width(phy, 8);
 401                 phy_set_drvdata(phy, usbphyc_phy);
 402
 403                 usbphyc->phys[port]->phy = phy;
 404                 usbphyc->phys[port]->usbphyc = usbphyc;
 405                 usbphyc->phys[port]->index = index;
 406                 usbphyc->phys[port]->active = false;
 407
 408                 port++;
 409         }
 410
 411         phy_provider = devm_of_phy_provider_register(dev,
 412                                                      stm32_usbphyc_of_xlate);
 413         if (IS_ERR(phy_provider)) {
 414                 ret = PTR_ERR(phy_provider);
 415                 dev_err(dev, "failed to register phy provider: %d\n", ret);
 416                 goto clk_disable;
 417         }
 418
 419         version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
 420         dev_info(dev, "registered rev:%lu.%lu\n",
 421                  FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
 422
 423         return 0;
 424
 425 put_child:
 426         of_node_put(child);
 427 clk_disable:
 428         clk_disable_unprepare(usbphyc->clk);
 429
 430         return ret;
 431 }
 432
 433 static int stm32_usbphyc_remove(struct platform_device *pdev)
 434 {
 435         struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
 436
 437         clk_disable_unprepare(usbphyc->clk);
 438
 439         return 0;
 440 }
 441
 442 static const struct of_device_id stm32_usbphyc_of_match[] = {
 443         { .compatible = "st,stm32mp1-usbphyc", },
 444         { },
 445 };
 446 MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
 447
 448 static struct platform_driver stm32_usbphyc_driver = {
 449         .probe = stm32_usbphyc_probe,
 450         .remove = stm32_usbphyc_remove,
 451         .driver = {
 452                 .of_match_table = stm32_usbphyc_of_match,
 453                 .name = "stm32-usbphyc",
 454         }
 455 };
 456 module_platform_driver(stm32_usbphyc_driver);
 457
 458 MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
 459 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
 460 MODULE_LICENSE("GPL v2");