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PM / Domains: Fix a warning message
[linux/fpc-iii.git] / drivers / pinctrl / intel / pinctrl-cherryview.c
blob30389f4ccab4935c20ddcbed2c5a543e77d33fc5
1 /*
2 * Cherryview/Braswell pinctrl driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 *
7 * This driver is based on the original Cherryview GPIO driver by
8 * Ning Li <ning.li@intel.com>
9 * Alan Cox <alan@linux.intel.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/acpi.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/platform_device.h>
28
29 #define CHV_INTSTAT 0x300
30 #define CHV_INTMASK 0x380
31
32 #define FAMILY_PAD_REGS_OFF 0x4400
33 #define FAMILY_PAD_REGS_SIZE 0x400
34 #define MAX_FAMILY_PAD_GPIO_NO 15
35 #define GPIO_REGS_SIZE 8
36
37 #define CHV_PADCTRL0 0x000
38 #define CHV_PADCTRL0_INTSEL_SHIFT 28
39 #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
40 #define CHV_PADCTRL0_TERM_UP BIT(23)
41 #define CHV_PADCTRL0_TERM_SHIFT 20
42 #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT)
43 #define CHV_PADCTRL0_TERM_20K 1
44 #define CHV_PADCTRL0_TERM_5K 2
45 #define CHV_PADCTRL0_TERM_1K 4
46 #define CHV_PADCTRL0_PMODE_SHIFT 16
47 #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT)
48 #define CHV_PADCTRL0_GPIOEN BIT(15)
49 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8
50 #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
51 #define CHV_PADCTRL0_GPIOCFG_GPIO 0
52 #define CHV_PADCTRL0_GPIOCFG_GPO 1
53 #define CHV_PADCTRL0_GPIOCFG_GPI 2
54 #define CHV_PADCTRL0_GPIOCFG_HIZ 3
55 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
56 #define CHV_PADCTRL0_GPIORXSTATE BIT(0)
57
58 #define CHV_PADCTRL1 0x004
59 #define CHV_PADCTRL1_CFGLOCK BIT(31)
60 #define CHV_PADCTRL1_INVRXTX_SHIFT 4
61 #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
62 #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
63 #define CHV_PADCTRL1_ODEN BIT(3)
64 #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
65 #define CHV_PADCTRL1_INTWAKECFG_MASK 7
66 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
67 #define CHV_PADCTRL1_INTWAKECFG_RISING 2
68 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3
69 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
70
71 /**
72 * struct chv_alternate_function - A per group or per pin alternate function
73 * @pin: Pin number (only used in per pin configs)
74 * @mode: Mode the pin should be set in
75 * @invert_oe: Invert OE for this pin
76 */
77 struct chv_alternate_function {
78 unsigned pin;
79 u8 mode;
80 bool invert_oe;
81 };
82
83 /**
84 * struct chv_pincgroup - describes a CHV pin group
85 * @name: Name of the group
86 * @pins: An array of pins in this group
87 * @npins: Number of pins in this group
88 * @altfunc: Alternate function applied to all pins in this group
89 * @overrides: Alternate function override per pin or %NULL if not used
90 * @noverrides: Number of per pin alternate function overrides if
91 * @overrides != NULL.
92 */
93 struct chv_pingroup {
94 const char *name;
95 const unsigned *pins;
96 size_t npins;
97 struct chv_alternate_function altfunc;
98 const struct chv_alternate_function *overrides;
99 size_t noverrides;
100 };
101
102 /**
103 * struct chv_function - A CHV pinmux function
104 * @name: Name of the function
105 * @groups: An array of groups for this function
106 * @ngroups: Number of groups in @groups
107 */
108 struct chv_function {
109 const char *name;
110 const char * const *groups;
111 size_t ngroups;
112 };
113
114 /**
115 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
116 * @base: Start pin number
117 * @npins: Number of pins in this range
118 */
119 struct chv_gpio_pinrange {
120 unsigned base;
121 unsigned npins;
122 };
123
124 /**
125 * struct chv_community - A community specific configuration
126 * @uid: ACPI _UID used to match the community
127 * @pins: All pins in this community
128 * @npins: Number of pins
129 * @groups: All groups in this community
130 * @ngroups: Number of groups
131 * @functions: All functions in this community
132 * @nfunctions: Number of functions
133 * @ngpios: Number of GPIOs in this community
134 * @gpio_ranges: An array of GPIO ranges in this community
135 * @ngpio_ranges: Number of GPIO ranges
136 * @ngpios: Total number of GPIOs in this community
137 * @nirqs: Total number of IRQs this community can generate
138 */
139 struct chv_community {
140 const char *uid;
141 const struct pinctrl_pin_desc *pins;
142 size_t npins;
143 const struct chv_pingroup *groups;
144 size_t ngroups;
145 const struct chv_function *functions;
146 size_t nfunctions;
147 const struct chv_gpio_pinrange *gpio_ranges;
148 size_t ngpio_ranges;
149 size_t ngpios;
150 size_t nirqs;
151 };
152
153 struct chv_pin_context {
154 u32 padctrl0;
155 u32 padctrl1;
156 };
157
158 /**
159 * struct chv_pinctrl - CHV pinctrl private structure
160 * @dev: Pointer to the parent device
161 * @pctldesc: Pin controller description
162 * @pctldev: Pointer to the pin controller device
163 * @chip: GPIO chip in this pin controller
164 * @regs: MMIO registers
165 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
166 * offset (in GPIO number space)
167 * @community: Community this pinctrl instance represents
168 *
169 * The first group in @groups is expected to contain all pins that can be
170 * used as GPIOs.
171 */
172 struct chv_pinctrl {
173 struct device *dev;
174 struct pinctrl_desc pctldesc;
175 struct pinctrl_dev *pctldev;
176 struct gpio_chip chip;
177 void __iomem *regs;
178 unsigned intr_lines[16];
179 const struct chv_community *community;
180 u32 saved_intmask;
181 struct chv_pin_context *saved_pin_context;
182 };
183
184 #define ALTERNATE_FUNCTION(p, m, i) \
185 { \
186 .pin = (p), \
187 .mode = (m), \
188 .invert_oe = (i), \
189 }
190
191 #define PIN_GROUP(n, p, m, i) \
192 { \
193 .name = (n), \
194 .pins = (p), \
195 .npins = ARRAY_SIZE((p)), \
196 .altfunc.mode = (m), \
197 .altfunc.invert_oe = (i), \
198 }
199
200 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \
201 { \
202 .name = (n), \
203 .pins = (p), \
204 .npins = ARRAY_SIZE((p)), \
205 .altfunc.mode = (m), \
206 .altfunc.invert_oe = (i), \
207 .overrides = (o), \
208 .noverrides = ARRAY_SIZE((o)), \
209 }
210
211 #define FUNCTION(n, g) \
212 { \
213 .name = (n), \
214 .groups = (g), \
215 .ngroups = ARRAY_SIZE((g)), \
216 }
217
218 #define GPIO_PINRANGE(start, end) \
219 { \
220 .base = (start), \
221 .npins = (end) - (start) + 1, \
222 }
223
224 static const struct pinctrl_pin_desc southwest_pins[] = {
225 PINCTRL_PIN(0, "FST_SPI_D2"),
226 PINCTRL_PIN(1, "FST_SPI_D0"),
227 PINCTRL_PIN(2, "FST_SPI_CLK"),
228 PINCTRL_PIN(3, "FST_SPI_D3"),
229 PINCTRL_PIN(4, "FST_SPI_CS1_B"),
230 PINCTRL_PIN(5, "FST_SPI_D1"),
231 PINCTRL_PIN(6, "FST_SPI_CS0_B"),
232 PINCTRL_PIN(7, "FST_SPI_CS2_B"),
233
234 PINCTRL_PIN(15, "UART1_RTS_B"),
235 PINCTRL_PIN(16, "UART1_RXD"),
236 PINCTRL_PIN(17, "UART2_RXD"),
237 PINCTRL_PIN(18, "UART1_CTS_B"),
238 PINCTRL_PIN(19, "UART2_RTS_B"),
239 PINCTRL_PIN(20, "UART1_TXD"),
240 PINCTRL_PIN(21, "UART2_TXD"),
241 PINCTRL_PIN(22, "UART2_CTS_B"),
242
243 PINCTRL_PIN(30, "MF_HDA_CLK"),
244 PINCTRL_PIN(31, "MF_HDA_RSTB"),
245 PINCTRL_PIN(32, "MF_HDA_SDIO"),
246 PINCTRL_PIN(33, "MF_HDA_SDO"),
247 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
248 PINCTRL_PIN(35, "MF_HDA_SYNC"),
249 PINCTRL_PIN(36, "MF_HDA_SDI1"),
250 PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
251
252 PINCTRL_PIN(45, "I2C5_SDA"),
253 PINCTRL_PIN(46, "I2C4_SDA"),
254 PINCTRL_PIN(47, "I2C6_SDA"),
255 PINCTRL_PIN(48, "I2C5_SCL"),
256 PINCTRL_PIN(49, "I2C_NFC_SDA"),
257 PINCTRL_PIN(50, "I2C4_SCL"),
258 PINCTRL_PIN(51, "I2C6_SCL"),
259 PINCTRL_PIN(52, "I2C_NFC_SCL"),
260
261 PINCTRL_PIN(60, "I2C1_SDA"),
262 PINCTRL_PIN(61, "I2C0_SDA"),
263 PINCTRL_PIN(62, "I2C2_SDA"),
264 PINCTRL_PIN(63, "I2C1_SCL"),
265 PINCTRL_PIN(64, "I2C3_SDA"),
266 PINCTRL_PIN(65, "I2C0_SCL"),
267 PINCTRL_PIN(66, "I2C2_SCL"),
268 PINCTRL_PIN(67, "I2C3_SCL"),
269
270 PINCTRL_PIN(75, "SATA_GP0"),
271 PINCTRL_PIN(76, "SATA_GP1"),
272 PINCTRL_PIN(77, "SATA_LEDN"),
273 PINCTRL_PIN(78, "SATA_GP2"),
274 PINCTRL_PIN(79, "MF_SMB_ALERTB"),
275 PINCTRL_PIN(80, "SATA_GP3"),
276 PINCTRL_PIN(81, "MF_SMB_CLK"),
277 PINCTRL_PIN(82, "MF_SMB_DATA"),
278
279 PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
280 PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
281 PINCTRL_PIN(92, "GP_SSP_2_CLK"),
282 PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
283 PINCTRL_PIN(94, "GP_SSP_2_RXD"),
284 PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
285 PINCTRL_PIN(96, "GP_SSP_2_FS"),
286 PINCTRL_PIN(97, "GP_SSP_2_TXD"),
287 };
288
289 static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
290 static const unsigned southwest_uart0_pins[] = { 16, 20 };
291 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
292 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
293 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
294 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
295 static const unsigned southwest_lpe_pins[] = {
296 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
297 };
298 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
299 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
300 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
301 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
302 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
303 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
304 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
305 static const unsigned southwest_smbus_pins[] = { 79, 81, 82 };
306 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
307
308 /* LPE I2S TXD pins need to have invert_oe set */
309 static const struct chv_alternate_function southwest_lpe_altfuncs[] = {
310 ALTERNATE_FUNCTION(30, 1, true),
311 ALTERNATE_FUNCTION(34, 1, true),
312 ALTERNATE_FUNCTION(97, 1, true),
313 };
314
315 /*
316 * Two spi3 chipselects are available in different mode than the main spi3
317 * functionality, which is using mode 1.
318 */
319 static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
320 ALTERNATE_FUNCTION(76, 3, false),
321 ALTERNATE_FUNCTION(80, 3, false),
322 };
323
324 static const struct chv_pingroup southwest_groups[] = {
325 PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false),
326 PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false),
327 PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false),
328 PIN_GROUP("hda_grp", southwest_hda_pins, 2, false),
329 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true),
330 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true),
331 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true),
332 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true),
333 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true),
334 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true),
335 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true),
336 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
337
338 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
339 southwest_lpe_altfuncs),
340 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false,
341 southwest_spi3_altfuncs),
342 };
343
344 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
345 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
346 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
347 static const char * const southwest_hda_groups[] = { "hda_grp" };
348 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
349 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
350 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
351 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
352 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
353 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
354 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
355 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
356 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
357 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
358
359 /*
360 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
361 * enabled only as GPIOs.
362 */
363 static const struct chv_function southwest_functions[] = {
364 FUNCTION("uart0", southwest_uart0_groups),
365 FUNCTION("uart1", southwest_uart1_groups),
366 FUNCTION("uart2", southwest_uart2_groups),
367 FUNCTION("hda", southwest_hda_groups),
368 FUNCTION("lpe", southwest_lpe_groups),
369 FUNCTION("i2c0", southwest_i2c0_groups),
370 FUNCTION("i2c1", southwest_i2c1_groups),
371 FUNCTION("i2c2", southwest_i2c2_groups),
372 FUNCTION("i2c3", southwest_i2c3_groups),
373 FUNCTION("i2c4", southwest_i2c4_groups),
374 FUNCTION("i2c5", southwest_i2c5_groups),
375 FUNCTION("i2c6", southwest_i2c6_groups),
376 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
377 FUNCTION("spi3", southwest_spi3_groups),
378 };
379
380 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = {
381 GPIO_PINRANGE(0, 7),
382 GPIO_PINRANGE(15, 22),
383 GPIO_PINRANGE(30, 37),
384 GPIO_PINRANGE(45, 52),
385 GPIO_PINRANGE(60, 67),
386 GPIO_PINRANGE(75, 82),
387 GPIO_PINRANGE(90, 97),
388 };
389
390 static const struct chv_community southwest_community = {
391 .uid = "1",
392 .pins = southwest_pins,
393 .npins = ARRAY_SIZE(southwest_pins),
394 .groups = southwest_groups,
395 .ngroups = ARRAY_SIZE(southwest_groups),
396 .functions = southwest_functions,
397 .nfunctions = ARRAY_SIZE(southwest_functions),
398 .gpio_ranges = southwest_gpio_ranges,
399 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
400 .ngpios = ARRAY_SIZE(southwest_pins),
401 /*
402 * Southwest community can benerate GPIO interrupts only for the
403 * first 8 interrupts. The upper half (8-15) can only be used to
404 * trigger GPEs.
405 */
406 .nirqs = 8,
407 };
408
409 static const struct pinctrl_pin_desc north_pins[] = {
410 PINCTRL_PIN(0, "GPIO_DFX_0"),
411 PINCTRL_PIN(1, "GPIO_DFX_3"),
412 PINCTRL_PIN(2, "GPIO_DFX_7"),
413 PINCTRL_PIN(3, "GPIO_DFX_1"),
414 PINCTRL_PIN(4, "GPIO_DFX_5"),
415 PINCTRL_PIN(5, "GPIO_DFX_4"),
416 PINCTRL_PIN(6, "GPIO_DFX_8"),
417 PINCTRL_PIN(7, "GPIO_DFX_2"),
418 PINCTRL_PIN(8, "GPIO_DFX_6"),
419
420 PINCTRL_PIN(15, "GPIO_SUS0"),
421 PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
422 PINCTRL_PIN(17, "GPIO_SUS3"),
423 PINCTRL_PIN(18, "GPIO_SUS7"),
424 PINCTRL_PIN(19, "GPIO_SUS1"),
425 PINCTRL_PIN(20, "GPIO_SUS5"),
426 PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
427 PINCTRL_PIN(22, "GPIO_SUS4"),
428 PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
429 PINCTRL_PIN(24, "GPIO_SUS2"),
430 PINCTRL_PIN(25, "GPIO_SUS6"),
431 PINCTRL_PIN(26, "CX_PREQ_B"),
432 PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
433
434 PINCTRL_PIN(30, "TRST_B"),
435 PINCTRL_PIN(31, "TCK"),
436 PINCTRL_PIN(32, "PROCHOT_B"),
437 PINCTRL_PIN(33, "SVIDO_DATA"),
438 PINCTRL_PIN(34, "TMS"),
439 PINCTRL_PIN(35, "CX_PRDY_B_2"),
440 PINCTRL_PIN(36, "TDO_2"),
441 PINCTRL_PIN(37, "CX_PRDY_B"),
442 PINCTRL_PIN(38, "SVIDO_ALERT_B"),
443 PINCTRL_PIN(39, "TDO"),
444 PINCTRL_PIN(40, "SVIDO_CLK"),
445 PINCTRL_PIN(41, "TDI"),
446
447 PINCTRL_PIN(45, "GP_CAMERASB_05"),
448 PINCTRL_PIN(46, "GP_CAMERASB_02"),
449 PINCTRL_PIN(47, "GP_CAMERASB_08"),
450 PINCTRL_PIN(48, "GP_CAMERASB_00"),
451 PINCTRL_PIN(49, "GP_CAMERASB_06"),
452 PINCTRL_PIN(50, "GP_CAMERASB_10"),
453 PINCTRL_PIN(51, "GP_CAMERASB_03"),
454 PINCTRL_PIN(52, "GP_CAMERASB_09"),
455 PINCTRL_PIN(53, "GP_CAMERASB_01"),
456 PINCTRL_PIN(54, "GP_CAMERASB_07"),
457 PINCTRL_PIN(55, "GP_CAMERASB_11"),
458 PINCTRL_PIN(56, "GP_CAMERASB_04"),
459
460 PINCTRL_PIN(60, "PANEL0_BKLTEN"),
461 PINCTRL_PIN(61, "HV_DDI0_HPD"),
462 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
463 PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
464 PINCTRL_PIN(64, "HV_DDI1_HPD"),
465 PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
466 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
467 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
468 PINCTRL_PIN(68, "HV_DDI2_HPD"),
469 PINCTRL_PIN(69, "PANEL1_VDDEN"),
470 PINCTRL_PIN(70, "PANEL1_BKLTEN"),
471 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
472 PINCTRL_PIN(72, "PANEL0_VDDEN"),
473 };
474
475 static const struct chv_gpio_pinrange north_gpio_ranges[] = {
476 GPIO_PINRANGE(0, 8),
477 GPIO_PINRANGE(15, 27),
478 GPIO_PINRANGE(30, 41),
479 GPIO_PINRANGE(45, 56),
480 GPIO_PINRANGE(60, 72),
481 };
482
483 static const struct chv_community north_community = {
484 .uid = "2",
485 .pins = north_pins,
486 .npins = ARRAY_SIZE(north_pins),
487 .gpio_ranges = north_gpio_ranges,
488 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
489 .ngpios = ARRAY_SIZE(north_pins),
490 /*
491 * North community can benerate GPIO interrupts only for the first
492 * 8 interrupts. The upper half (8-15) can only be used to trigger
493 * GPEs.
494 */
495 .nirqs = 8,
496 };
497
498 static const struct pinctrl_pin_desc east_pins[] = {
499 PINCTRL_PIN(0, "PMU_SLP_S3_B"),
500 PINCTRL_PIN(1, "PMU_BATLOW_B"),
501 PINCTRL_PIN(2, "SUS_STAT_B"),
502 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
503 PINCTRL_PIN(4, "PMU_AC_PRESENT"),
504 PINCTRL_PIN(5, "PMU_PLTRST_B"),
505 PINCTRL_PIN(6, "PMU_SUSCLK"),
506 PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
507 PINCTRL_PIN(8, "PMU_PWRBTN_B"),
508 PINCTRL_PIN(9, "PMU_SLP_S4_B"),
509 PINCTRL_PIN(10, "PMU_WAKE_B"),
510 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
511
512 PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
513 PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
514 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
515 PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
516 PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
517 PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
518 PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
519 PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
520 PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
521 PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
522 PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
523 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
524 };
525
526 static const struct chv_gpio_pinrange east_gpio_ranges[] = {
527 GPIO_PINRANGE(0, 11),
528 GPIO_PINRANGE(15, 26),
529 };
530
531 static const struct chv_community east_community = {
532 .uid = "3",
533 .pins = east_pins,
534 .npins = ARRAY_SIZE(east_pins),
535 .gpio_ranges = east_gpio_ranges,
536 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
537 .ngpios = ARRAY_SIZE(east_pins),
538 .nirqs = 16,
539 };
540
541 static const struct pinctrl_pin_desc southeast_pins[] = {
542 PINCTRL_PIN(0, "MF_PLT_CLK0"),
543 PINCTRL_PIN(1, "PWM1"),
544 PINCTRL_PIN(2, "MF_PLT_CLK1"),
545 PINCTRL_PIN(3, "MF_PLT_CLK4"),
546 PINCTRL_PIN(4, "MF_PLT_CLK3"),
547 PINCTRL_PIN(5, "PWM0"),
548 PINCTRL_PIN(6, "MF_PLT_CLK5"),
549 PINCTRL_PIN(7, "MF_PLT_CLK2"),
550
551 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
552 PINCTRL_PIN(16, "SDMMC1_CLK"),
553 PINCTRL_PIN(17, "SDMMC1_D0"),
554 PINCTRL_PIN(18, "SDMMC2_D1"),
555 PINCTRL_PIN(19, "SDMMC2_CLK"),
556 PINCTRL_PIN(20, "SDMMC1_D2"),
557 PINCTRL_PIN(21, "SDMMC2_D2"),
558 PINCTRL_PIN(22, "SDMMC2_CMD"),
559 PINCTRL_PIN(23, "SDMMC1_CMD"),
560 PINCTRL_PIN(24, "SDMMC1_D1"),
561 PINCTRL_PIN(25, "SDMMC2_D0"),
562 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
563
564 PINCTRL_PIN(30, "SDMMC3_D1"),
565 PINCTRL_PIN(31, "SDMMC3_CLK"),
566 PINCTRL_PIN(32, "SDMMC3_D3"),
567 PINCTRL_PIN(33, "SDMMC3_D2"),
568 PINCTRL_PIN(34, "SDMMC3_CMD"),
569 PINCTRL_PIN(35, "SDMMC3_D0"),
570
571 PINCTRL_PIN(45, "MF_LPC_AD2"),
572 PINCTRL_PIN(46, "LPC_CLKRUNB"),
573 PINCTRL_PIN(47, "MF_LPC_AD0"),
574 PINCTRL_PIN(48, "LPC_FRAMEB"),
575 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
576 PINCTRL_PIN(50, "MF_LPC_AD3"),
577 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
578 PINCTRL_PIN(52, "MF_LPC_AD1"),
579
580 PINCTRL_PIN(60, "SPI1_MISO"),
581 PINCTRL_PIN(61, "SPI1_CSO_B"),
582 PINCTRL_PIN(62, "SPI1_CLK"),
583 PINCTRL_PIN(63, "MMC1_D6"),
584 PINCTRL_PIN(64, "SPI1_MOSI"),
585 PINCTRL_PIN(65, "MMC1_D5"),
586 PINCTRL_PIN(66, "SPI1_CS1_B"),
587 PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
588 PINCTRL_PIN(68, "MMC1_D7"),
589 PINCTRL_PIN(69, "MMC1_RCLK"),
590
591 PINCTRL_PIN(75, "USB_OC1_B"),
592 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
593 PINCTRL_PIN(77, "GPIO_ALERT"),
594 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
595 PINCTRL_PIN(79, "ILB_SERIRQ"),
596 PINCTRL_PIN(80, "USB_OC0_B"),
597 PINCTRL_PIN(81, "SDMMC3_CD_B"),
598 PINCTRL_PIN(82, "SPKR"),
599 PINCTRL_PIN(83, "SUSPWRDNACK"),
600 PINCTRL_PIN(84, "SPARE_PIN"),
601 PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
602 };
603
604 static const unsigned southeast_pwm0_pins[] = { 5 };
605 static const unsigned southeast_pwm1_pins[] = { 1 };
606 static const unsigned southeast_sdmmc1_pins[] = {
607 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
608 };
609 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
610 static const unsigned southeast_sdmmc3_pins[] = {
611 30, 31, 32, 33, 34, 35, 78, 81, 85,
612 };
613 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
614 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
615
616 static const struct chv_pingroup southeast_groups[] = {
617 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false),
618 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false),
619 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
620 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
621 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
622 PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false),
623 PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false),
624 };
625
626 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
627 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
628 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
629 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
630 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
631 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
632 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
633
634 static const struct chv_function southeast_functions[] = {
635 FUNCTION("pwm0", southeast_pwm0_groups),
636 FUNCTION("pwm1", southeast_pwm1_groups),
637 FUNCTION("sdmmc1", southeast_sdmmc1_groups),
638 FUNCTION("sdmmc2", southeast_sdmmc2_groups),
639 FUNCTION("sdmmc3", southeast_sdmmc3_groups),
640 FUNCTION("spi1", southeast_spi1_groups),
641 FUNCTION("spi2", southeast_spi2_groups),
642 };
643
644 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = {
645 GPIO_PINRANGE(0, 7),
646 GPIO_PINRANGE(15, 26),
647 GPIO_PINRANGE(30, 35),
648 GPIO_PINRANGE(45, 52),
649 GPIO_PINRANGE(60, 69),
650 GPIO_PINRANGE(75, 85),
651 };
652
653 static const struct chv_community southeast_community = {
654 .uid = "4",
655 .pins = southeast_pins,
656 .npins = ARRAY_SIZE(southeast_pins),
657 .groups = southeast_groups,
658 .ngroups = ARRAY_SIZE(southeast_groups),
659 .functions = southeast_functions,
660 .nfunctions = ARRAY_SIZE(southeast_functions),
661 .gpio_ranges = southeast_gpio_ranges,
662 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
663 .ngpios = ARRAY_SIZE(southeast_pins),
664 .nirqs = 16,
665 };
666
667 static const struct chv_community *chv_communities[] = {
668 &southwest_community,
669 &north_community,
670 &east_community,
671 &southeast_community,
672 };
673
674 /*
675 * Lock to serialize register accesses
676 *
677 * Due to a silicon issue, a shared lock must be used to prevent
678 * concurrent accesses across the 4 GPIO controllers.
679 *
680 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
681 * errata #CHT34, for further information.
682 */
683 static DEFINE_RAW_SPINLOCK(chv_lock);
684
685 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset,
686 unsigned reg)
687 {
688 unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
689 unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
690
691 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
692 GPIO_REGS_SIZE * pad_no;
693
694 return pctrl->regs + offset + reg;
695 }
696
697 static void chv_writel(u32 value, void __iomem *reg)
698 {
699 writel(value, reg);
700 /* simple readback to confirm the bus transferring done */
701 readl(reg);
702 }
703
704 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
705 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset)
706 {
707 void __iomem *reg;
708
709 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
710 return readl(reg) & CHV_PADCTRL1_CFGLOCK;
711 }
712
713 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
714 {
715 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
716
717 return pctrl->community->ngroups;
718 }
719
720 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
721 unsigned group)
722 {
723 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
724
725 return pctrl->community->groups[group].name;
726 }
727
728 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
729 const unsigned **pins, unsigned *npins)
730 {
731 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
732
733 *pins = pctrl->community->groups[group].pins;
734 *npins = pctrl->community->groups[group].npins;
735 return 0;
736 }
737
738 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
739 unsigned offset)
740 {
741 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
742 unsigned long flags;
743 u32 ctrl0, ctrl1;
744 bool locked;
745
746 raw_spin_lock_irqsave(&chv_lock, flags);
747
748 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
749 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
750 locked = chv_pad_locked(pctrl, offset);
751
752 raw_spin_unlock_irqrestore(&chv_lock, flags);
753
754 if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
755 seq_puts(s, "GPIO ");
756 } else {
757 u32 mode;
758
759 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
760 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
761
762 seq_printf(s, "mode %d ", mode);
763 }
764
765 seq_printf(s, "ctrl0 0x%08x ctrl1 0x%08x", ctrl0, ctrl1);
766
767 if (locked)
768 seq_puts(s, " [LOCKED]");
769 }
770
771 static const struct pinctrl_ops chv_pinctrl_ops = {
772 .get_groups_count = chv_get_groups_count,
773 .get_group_name = chv_get_group_name,
774 .get_group_pins = chv_get_group_pins,
775 .pin_dbg_show = chv_pin_dbg_show,
776 };
777
778 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
779 {
780 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
781
782 return pctrl->community->nfunctions;
783 }
784
785 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
786 unsigned function)
787 {
788 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
789
790 return pctrl->community->functions[function].name;
791 }
792
793 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
794 unsigned function,
795 const char * const **groups,
796 unsigned * const ngroups)
797 {
798 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
799
800 *groups = pctrl->community->functions[function].groups;
801 *ngroups = pctrl->community->functions[function].ngroups;
802 return 0;
803 }
804
805 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
806 unsigned group)
807 {
808 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
809 const struct chv_pingroup *grp;
810 unsigned long flags;
811 int i;
812
813 grp = &pctrl->community->groups[group];
814
815 raw_spin_lock_irqsave(&chv_lock, flags);
816
817 /* Check first that the pad is not locked */
818 for (i = 0; i < grp->npins; i++) {
819 if (chv_pad_locked(pctrl, grp->pins[i])) {
820 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
821 grp->pins[i]);
822 raw_spin_unlock_irqrestore(&chv_lock, flags);
823 return -EBUSY;
824 }
825 }
826
827 for (i = 0; i < grp->npins; i++) {
828 const struct chv_alternate_function *altfunc = &grp->altfunc;
829 int pin = grp->pins[i];
830 void __iomem *reg;
831 u32 value;
832
833 /* Check if there is pin-specific config */
834 if (grp->overrides) {
835 int j;
836
837 for (j = 0; j < grp->noverrides; j++) {
838 if (grp->overrides[j].pin == pin) {
839 altfunc = &grp->overrides[j];
840 break;
841 }
842 }
843 }
844
845 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
846 value = readl(reg);
847 /* Disable GPIO mode */
848 value &= ~CHV_PADCTRL0_GPIOEN;
849 /* Set to desired mode */
850 value &= ~CHV_PADCTRL0_PMODE_MASK;
851 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT;
852 chv_writel(value, reg);
853
854 /* Update for invert_oe */
855 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
856 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
857 if (altfunc->invert_oe)
858 value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
859 chv_writel(value, reg);
860
861 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
862 pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
863 }
864
865 raw_spin_unlock_irqrestore(&chv_lock, flags);
866
867 return 0;
868 }
869
870 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
871 struct pinctrl_gpio_range *range,
872 unsigned offset)
873 {
874 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
875 unsigned long flags;
876 void __iomem *reg;
877 u32 value;
878
879 raw_spin_lock_irqsave(&chv_lock, flags);
880
881 if (chv_pad_locked(pctrl, offset)) {
882 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
883 if (!(value & CHV_PADCTRL0_GPIOEN)) {
884 /* Locked so cannot enable */
885 raw_spin_unlock_irqrestore(&chv_lock, flags);
886 return -EBUSY;
887 }
888 } else {
889 int i;
890
891 /* Reset the interrupt mapping */
892 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
893 if (pctrl->intr_lines[i] == offset) {
894 pctrl->intr_lines[i] = 0;
895 break;
896 }
897 }
898
899 /* Disable interrupt generation */
900 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
901 value = readl(reg);
902 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
903 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
904 chv_writel(value, reg);
905
906 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
907 value = readl(reg);
908
909 /*
910 * If the pin is in HiZ mode (both TX and RX buffers are
911 * disabled) we turn it to be input now.
912 */
913 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
914 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
915 value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
916 value |= CHV_PADCTRL0_GPIOCFG_GPI <<
917 CHV_PADCTRL0_GPIOCFG_SHIFT;
918 }
919
920 /* Switch to a GPIO mode */
921 value |= CHV_PADCTRL0_GPIOEN;
922 chv_writel(value, reg);
923 }
924
925 raw_spin_unlock_irqrestore(&chv_lock, flags);
926
927 return 0;
928 }
929
930 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
931 struct pinctrl_gpio_range *range,
932 unsigned offset)
933 {
934 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
935 unsigned long flags;
936 void __iomem *reg;
937 u32 value;
938
939 raw_spin_lock_irqsave(&chv_lock, flags);
940
941 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
942 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
943 chv_writel(value, reg);
944
945 raw_spin_unlock_irqrestore(&chv_lock, flags);
946 }
947
948 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
949 struct pinctrl_gpio_range *range,
950 unsigned offset, bool input)
951 {
952 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
953 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
954 unsigned long flags;
955 u32 ctrl0;
956
957 raw_spin_lock_irqsave(&chv_lock, flags);
958
959 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
960 if (input)
961 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
962 else
963 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
964 chv_writel(ctrl0, reg);
965
966 raw_spin_unlock_irqrestore(&chv_lock, flags);
967
968 return 0;
969 }
970
971 static const struct pinmux_ops chv_pinmux_ops = {
972 .get_functions_count = chv_get_functions_count,
973 .get_function_name = chv_get_function_name,
974 .get_function_groups = chv_get_function_groups,
975 .set_mux = chv_pinmux_set_mux,
976 .gpio_request_enable = chv_gpio_request_enable,
977 .gpio_disable_free = chv_gpio_disable_free,
978 .gpio_set_direction = chv_gpio_set_direction,
979 };
980
981 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
982 unsigned long *config)
983 {
984 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
985 enum pin_config_param param = pinconf_to_config_param(*config);
986 unsigned long flags;
987 u32 ctrl0, ctrl1;
988 u16 arg = 0;
989 u32 term;
990
991 raw_spin_lock_irqsave(&chv_lock, flags);
992 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
993 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
994 raw_spin_unlock_irqrestore(&chv_lock, flags);
995
996 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
997
998 switch (param) {
999 case PIN_CONFIG_BIAS_DISABLE:
1000 if (term)
1001 return -EINVAL;
1002 break;
1003
1004 case PIN_CONFIG_BIAS_PULL_UP:
1005 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
1006 return -EINVAL;
1007
1008 switch (term) {
1009 case CHV_PADCTRL0_TERM_20K:
1010 arg = 20000;
1011 break;
1012 case CHV_PADCTRL0_TERM_5K:
1013 arg = 5000;
1014 break;
1015 case CHV_PADCTRL0_TERM_1K:
1016 arg = 1000;
1017 break;
1018 }
1019
1020 break;
1021
1022 case PIN_CONFIG_BIAS_PULL_DOWN:
1023 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
1024 return -EINVAL;
1025
1026 switch (term) {
1027 case CHV_PADCTRL0_TERM_20K:
1028 arg = 20000;
1029 break;
1030 case CHV_PADCTRL0_TERM_5K:
1031 arg = 5000;
1032 break;
1033 }
1034
1035 break;
1036
1037 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1038 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
1039 return -EINVAL;
1040 break;
1041
1042 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
1043 u32 cfg;
1044
1045 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1046 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1047 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
1048 return -EINVAL;
1049
1050 break;
1051 }
1052
1053 default:
1054 return -ENOTSUPP;
1055 }
1056
1057 *config = pinconf_to_config_packed(param, arg);
1058 return 0;
1059 }
1060
1061 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
1062 enum pin_config_param param, u16 arg)
1063 {
1064 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1065 unsigned long flags;
1066 u32 ctrl0, pull;
1067
1068 raw_spin_lock_irqsave(&chv_lock, flags);
1069 ctrl0 = readl(reg);
1070
1071 switch (param) {
1072 case PIN_CONFIG_BIAS_DISABLE:
1073 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1074 break;
1075
1076 case PIN_CONFIG_BIAS_PULL_UP:
1077 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1078
1079 switch (arg) {
1080 case 1000:
1081 /* For 1k there is only pull up */
1082 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1083 break;
1084 case 5000:
1085 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1086 break;
1087 case 20000:
1088 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1089 break;
1090 default:
1091 raw_spin_unlock_irqrestore(&chv_lock, flags);
1092 return -EINVAL;
1093 }
1094
1095 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1096 break;
1097
1098 case PIN_CONFIG_BIAS_PULL_DOWN:
1099 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1100
1101 switch (arg) {
1102 case 5000:
1103 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1104 break;
1105 case 20000:
1106 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1107 break;
1108 default:
1109 raw_spin_unlock_irqrestore(&chv_lock, flags);
1110 return -EINVAL;
1111 }
1112
1113 ctrl0 |= pull;
1114 break;
1115
1116 default:
1117 raw_spin_unlock_irqrestore(&chv_lock, flags);
1118 return -EINVAL;
1119 }
1120
1121 chv_writel(ctrl0, reg);
1122 raw_spin_unlock_irqrestore(&chv_lock, flags);
1123
1124 return 0;
1125 }
1126
1127 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1128 bool enable)
1129 {
1130 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1131 unsigned long flags;
1132 u32 ctrl1;
1133
1134 raw_spin_lock_irqsave(&chv_lock, flags);
1135 ctrl1 = readl(reg);
1136
1137 if (enable)
1138 ctrl1 |= CHV_PADCTRL1_ODEN;
1139 else
1140 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1141
1142 chv_writel(ctrl1, reg);
1143 raw_spin_unlock_irqrestore(&chv_lock, flags);
1144
1145 return 0;
1146 }
1147
1148 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1149 unsigned long *configs, unsigned nconfigs)
1150 {
1151 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1152 enum pin_config_param param;
1153 int i, ret;
1154 u16 arg;
1155
1156 if (chv_pad_locked(pctrl, pin))
1157 return -EBUSY;
1158
1159 for (i = 0; i < nconfigs; i++) {
1160 param = pinconf_to_config_param(configs[i]);
1161 arg = pinconf_to_config_argument(configs[i]);
1162
1163 switch (param) {
1164 case PIN_CONFIG_BIAS_DISABLE:
1165 case PIN_CONFIG_BIAS_PULL_UP:
1166 case PIN_CONFIG_BIAS_PULL_DOWN:
1167 ret = chv_config_set_pull(pctrl, pin, param, arg);
1168 if (ret)
1169 return ret;
1170 break;
1171
1172 case PIN_CONFIG_DRIVE_PUSH_PULL:
1173 ret = chv_config_set_oden(pctrl, pin, false);
1174 if (ret)
1175 return ret;
1176 break;
1177
1178 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1179 ret = chv_config_set_oden(pctrl, pin, true);
1180 if (ret)
1181 return ret;
1182 break;
1183
1184 default:
1185 return -ENOTSUPP;
1186 }
1187
1188 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1189 param, arg);
1190 }
1191
1192 return 0;
1193 }
1194
1195 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1196 unsigned int group,
1197 unsigned long *config)
1198 {
1199 const unsigned int *pins;
1200 unsigned int npins;
1201 int ret;
1202
1203 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1204 if (ret)
1205 return ret;
1206
1207 ret = chv_config_get(pctldev, pins[0], config);
1208 if (ret)
1209 return ret;
1210
1211 return 0;
1212 }
1213
1214 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1215 unsigned int group, unsigned long *configs,
1216 unsigned int num_configs)
1217 {
1218 const unsigned int *pins;
1219 unsigned int npins;
1220 int i, ret;
1221
1222 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1223 if (ret)
1224 return ret;
1225
1226 for (i = 0; i < npins; i++) {
1227 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1228 if (ret)
1229 return ret;
1230 }
1231
1232 return 0;
1233 }
1234
1235 static const struct pinconf_ops chv_pinconf_ops = {
1236 .is_generic = true,
1237 .pin_config_set = chv_config_set,
1238 .pin_config_get = chv_config_get,
1239 .pin_config_group_get = chv_config_group_get,
1240 .pin_config_group_set = chv_config_group_set,
1241 };
1242
1243 static struct pinctrl_desc chv_pinctrl_desc = {
1244 .pctlops = &chv_pinctrl_ops,
1245 .pmxops = &chv_pinmux_ops,
1246 .confops = &chv_pinconf_ops,
1247 .owner = THIS_MODULE,
1248 };
1249
1250 static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl,
1251 unsigned offset)
1252 {
1253 return pctrl->community->pins[offset].number;
1254 }
1255
1256 static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
1257 {
1258 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1259 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1260 unsigned long flags;
1261 u32 ctrl0, cfg;
1262
1263 raw_spin_lock_irqsave(&chv_lock, flags);
1264 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1265 raw_spin_unlock_irqrestore(&chv_lock, flags);
1266
1267 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1268 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1269
1270 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1271 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1272 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1273 }
1274
1275 static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1276 {
1277 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1278 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
1279 unsigned long flags;
1280 void __iomem *reg;
1281 u32 ctrl0;
1282
1283 raw_spin_lock_irqsave(&chv_lock, flags);
1284
1285 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1286 ctrl0 = readl(reg);
1287
1288 if (value)
1289 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1290 else
1291 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1292
1293 chv_writel(ctrl0, reg);
1294
1295 raw_spin_unlock_irqrestore(&chv_lock, flags);
1296 }
1297
1298 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1299 {
1300 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1301 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
1302 u32 ctrl0, direction;
1303 unsigned long flags;
1304
1305 raw_spin_lock_irqsave(&chv_lock, flags);
1306 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1307 raw_spin_unlock_irqrestore(&chv_lock, flags);
1308
1309 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1310 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1311
1312 return direction != CHV_PADCTRL0_GPIOCFG_GPO;
1313 }
1314
1315 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1316 {
1317 return pinctrl_gpio_direction_input(chip->base + offset);
1318 }
1319
1320 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1321 int value)
1322 {
1323 chv_gpio_set(chip, offset, value);
1324 return pinctrl_gpio_direction_output(chip->base + offset);
1325 }
1326
1327 static const struct gpio_chip chv_gpio_chip = {
1328 .owner = THIS_MODULE,
1329 .request = gpiochip_generic_request,
1330 .free = gpiochip_generic_free,
1331 .get_direction = chv_gpio_get_direction,
1332 .direction_input = chv_gpio_direction_input,
1333 .direction_output = chv_gpio_direction_output,
1334 .get = chv_gpio_get,
1335 .set = chv_gpio_set,
1336 };
1337
1338 static void chv_gpio_irq_ack(struct irq_data *d)
1339 {
1340 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1341 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1342 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
1343 u32 intr_line;
1344
1345 raw_spin_lock(&chv_lock);
1346
1347 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1348 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1349 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1350 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1351
1352 raw_spin_unlock(&chv_lock);
1353 }
1354
1355 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1356 {
1357 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1358 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1359 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
1360 u32 value, intr_line;
1361 unsigned long flags;
1362
1363 raw_spin_lock_irqsave(&chv_lock, flags);
1364
1365 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1366 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1367 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1368
1369 value = readl(pctrl->regs + CHV_INTMASK);
1370 if (mask)
1371 value &= ~BIT(intr_line);
1372 else
1373 value |= BIT(intr_line);
1374 chv_writel(value, pctrl->regs + CHV_INTMASK);
1375
1376 raw_spin_unlock_irqrestore(&chv_lock, flags);
1377 }
1378
1379 static void chv_gpio_irq_mask(struct irq_data *d)
1380 {
1381 chv_gpio_irq_mask_unmask(d, true);
1382 }
1383
1384 static void chv_gpio_irq_unmask(struct irq_data *d)
1385 {
1386 chv_gpio_irq_mask_unmask(d, false);
1387 }
1388
1389 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1390 {
1391 /*
1392 * Check if the interrupt has been requested with 0 as triggering
1393 * type. In that case it is assumed that the current values
1394 * programmed to the hardware are used (e.g BIOS configured
1395 * defaults).
1396 *
1397 * In that case ->irq_set_type() will never be called so we need to
1398 * read back the values from hardware now, set correct flow handler
1399 * and update mappings before the interrupt is being used.
1400 */
1401 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1402 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1403 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1404 unsigned offset = irqd_to_hwirq(d);
1405 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1406 irq_flow_handler_t handler;
1407 unsigned long flags;
1408 u32 intsel, value;
1409
1410 raw_spin_lock_irqsave(&chv_lock, flags);
1411 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1412 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1413 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1414
1415 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1416 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1417 handler = handle_level_irq;
1418 else
1419 handler = handle_edge_irq;
1420
1421 if (!pctrl->intr_lines[intsel]) {
1422 irq_set_handler_locked(d, handler);
1423 pctrl->intr_lines[intsel] = offset;
1424 }
1425 raw_spin_unlock_irqrestore(&chv_lock, flags);
1426 }
1427
1428 chv_gpio_irq_unmask(d);
1429 return 0;
1430 }
1431
1432 static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
1433 {
1434 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1435 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1436 unsigned offset = irqd_to_hwirq(d);
1437 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1438 unsigned long flags;
1439 u32 value;
1440
1441 raw_spin_lock_irqsave(&chv_lock, flags);
1442
1443 /*
1444 * Pins which can be used as shared interrupt are configured in
1445 * BIOS. Driver trusts BIOS configurations and assigns different
1446 * handler according to the irq type.
1447 *
1448 * Driver needs to save the mapping between each pin and
1449 * its interrupt line.
1450 * 1. If the pin cfg is locked in BIOS:
1451 * Trust BIOS has programmed IntWakeCfg bits correctly,
1452 * driver just needs to save the mapping.
1453 * 2. If the pin cfg is not locked in BIOS:
1454 * Driver programs the IntWakeCfg bits and save the mapping.
1455 */
1456 if (!chv_pad_locked(pctrl, pin)) {
1457 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1458
1459 value = readl(reg);
1460 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1461 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1462
1463 if (type & IRQ_TYPE_EDGE_BOTH) {
1464 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1465 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1466 else if (type & IRQ_TYPE_EDGE_RISING)
1467 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1468 else if (type & IRQ_TYPE_EDGE_FALLING)
1469 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1470 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1471 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1472 if (type & IRQ_TYPE_LEVEL_LOW)
1473 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1474 }
1475
1476 chv_writel(value, reg);
1477 }
1478
1479 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1480 value &= CHV_PADCTRL0_INTSEL_MASK;
1481 value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1482
1483 pctrl->intr_lines[value] = offset;
1484
1485 if (type & IRQ_TYPE_EDGE_BOTH)
1486 irq_set_handler_locked(d, handle_edge_irq);
1487 else if (type & IRQ_TYPE_LEVEL_MASK)
1488 irq_set_handler_locked(d, handle_level_irq);
1489
1490 raw_spin_unlock_irqrestore(&chv_lock, flags);
1491
1492 return 0;
1493 }
1494
1495 static struct irq_chip chv_gpio_irqchip = {
1496 .name = "chv-gpio",
1497 .irq_startup = chv_gpio_irq_startup,
1498 .irq_ack = chv_gpio_irq_ack,
1499 .irq_mask = chv_gpio_irq_mask,
1500 .irq_unmask = chv_gpio_irq_unmask,
1501 .irq_set_type = chv_gpio_irq_type,
1502 .flags = IRQCHIP_SKIP_SET_WAKE,
1503 };
1504
1505 static void chv_gpio_irq_handler(struct irq_desc *desc)
1506 {
1507 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1508 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1509 struct irq_chip *chip = irq_desc_get_chip(desc);
1510 unsigned long pending;
1511 u32 intr_line;
1512
1513 chained_irq_enter(chip, desc);
1514
1515 pending = readl(pctrl->regs + CHV_INTSTAT);
1516 for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
1517 unsigned irq, offset;
1518
1519 offset = pctrl->intr_lines[intr_line];
1520 irq = irq_find_mapping(gc->irqdomain, offset);
1521 generic_handle_irq(irq);
1522 }
1523
1524 chained_irq_exit(chip, desc);
1525 }
1526
1527 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1528 {
1529 const struct chv_gpio_pinrange *range;
1530 struct gpio_chip *chip = &pctrl->chip;
1531 int ret, i, offset;
1532
1533 *chip = chv_gpio_chip;
1534
1535 chip->ngpio = pctrl->community->ngpios;
1536 chip->label = dev_name(pctrl->dev);
1537 chip->parent = pctrl->dev;
1538 chip->base = -1;
1539 chip->irq_need_valid_mask = true;
1540
1541 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1542 if (ret) {
1543 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1544 return ret;
1545 }
1546
1547 for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) {
1548 range = &pctrl->community->gpio_ranges[i];
1549 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset,
1550 range->base, range->npins);
1551 if (ret) {
1552 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1553 return ret;
1554 }
1555
1556 offset += range->npins;
1557 }
1558
1559 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1560 for (i = 0; i < pctrl->community->npins; i++) {
1561 const struct pinctrl_pin_desc *desc;
1562 u32 intsel;
1563
1564 desc = &pctrl->community->pins[i];
1565
1566 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1567 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1568 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1569
1570 if (intsel >= pctrl->community->nirqs)
1571 clear_bit(i, chip->irq_valid_mask);
1572 }
1573
1574 /* Clear all interrupts */
1575 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1576
1577 ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,
1578 handle_bad_irq, IRQ_TYPE_NONE);
1579 if (ret) {
1580 dev_err(pctrl->dev, "failed to add IRQ chip\n");
1581 return ret;
1582 }
1583
1584 gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq,
1585 chv_gpio_irq_handler);
1586 return 0;
1587 }
1588
1589 static int chv_pinctrl_probe(struct platform_device *pdev)
1590 {
1591 struct chv_pinctrl *pctrl;
1592 struct acpi_device *adev;
1593 struct resource *res;
1594 int ret, irq, i;
1595
1596 adev = ACPI_COMPANION(&pdev->dev);
1597 if (!adev)
1598 return -ENODEV;
1599
1600 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1601 if (!pctrl)
1602 return -ENOMEM;
1603
1604 for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1605 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1606 pctrl->community = chv_communities[i];
1607 break;
1608 }
1609 if (i == ARRAY_SIZE(chv_communities))
1610 return -ENODEV;
1611
1612 pctrl->dev = &pdev->dev;
1613
1614 #ifdef CONFIG_PM_SLEEP
1615 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1616 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1617 GFP_KERNEL);
1618 if (!pctrl->saved_pin_context)
1619 return -ENOMEM;
1620 #endif
1621
1622 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1623 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1624 if (IS_ERR(pctrl->regs))
1625 return PTR_ERR(pctrl->regs);
1626
1627 irq = platform_get_irq(pdev, 0);
1628 if (irq < 0) {
1629 dev_err(&pdev->dev, "failed to get interrupt number\n");
1630 return irq;
1631 }
1632
1633 pctrl->pctldesc = chv_pinctrl_desc;
1634 pctrl->pctldesc.name = dev_name(&pdev->dev);
1635 pctrl->pctldesc.pins = pctrl->community->pins;
1636 pctrl->pctldesc.npins = pctrl->community->npins;
1637
1638 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1639 pctrl);
1640 if (IS_ERR(pctrl->pctldev)) {
1641 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1642 return PTR_ERR(pctrl->pctldev);
1643 }
1644
1645 ret = chv_gpio_probe(pctrl, irq);
1646 if (ret)
1647 return ret;
1648
1649 platform_set_drvdata(pdev, pctrl);
1650
1651 return 0;
1652 }
1653
1654 #ifdef CONFIG_PM_SLEEP
1655 static int chv_pinctrl_suspend(struct device *dev)
1656 {
1657 struct platform_device *pdev = to_platform_device(dev);
1658 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1659 int i;
1660
1661 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1662
1663 for (i = 0; i < pctrl->community->npins; i++) {
1664 const struct pinctrl_pin_desc *desc;
1665 struct chv_pin_context *ctx;
1666 void __iomem *reg;
1667
1668 desc = &pctrl->community->pins[i];
1669 if (chv_pad_locked(pctrl, desc->number))
1670 continue;
1671
1672 ctx = &pctrl->saved_pin_context[i];
1673
1674 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1675 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1676
1677 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1678 ctx->padctrl1 = readl(reg);
1679 }
1680
1681 return 0;
1682 }
1683
1684 static int chv_pinctrl_resume(struct device *dev)
1685 {
1686 struct platform_device *pdev = to_platform_device(dev);
1687 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1688 int i;
1689
1690 /*
1691 * Mask all interrupts before restoring per-pin configuration
1692 * registers because we don't know in which state BIOS left them
1693 * upon exiting suspend.
1694 */
1695 chv_writel(0, pctrl->regs + CHV_INTMASK);
1696
1697 for (i = 0; i < pctrl->community->npins; i++) {
1698 const struct pinctrl_pin_desc *desc;
1699 const struct chv_pin_context *ctx;
1700 void __iomem *reg;
1701 u32 val;
1702
1703 desc = &pctrl->community->pins[i];
1704 if (chv_pad_locked(pctrl, desc->number))
1705 continue;
1706
1707 ctx = &pctrl->saved_pin_context[i];
1708
1709 /* Only restore if our saved state differs from the current */
1710 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1711 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1712 if (ctx->padctrl0 != val) {
1713 chv_writel(ctx->padctrl0, reg);
1714 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1715 desc->number, readl(reg));
1716 }
1717
1718 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1719 val = readl(reg);
1720 if (ctx->padctrl1 != val) {
1721 chv_writel(ctx->padctrl1, reg);
1722 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1723 desc->number, readl(reg));
1724 }
1725 }
1726
1727 /*
1728 * Now that all pins are restored to known state, we can restore
1729 * the interrupt mask register as well.
1730 */
1731 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1732 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1733
1734 return 0;
1735 }
1736 #endif
1737
1738 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1739 SET_LATE_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend, chv_pinctrl_resume)
1740 };
1741
1742 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1743 { "INT33FF" },
1744 { }
1745 };
1746 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1747
1748 static struct platform_driver chv_pinctrl_driver = {
1749 .probe = chv_pinctrl_probe,
1750 .driver = {
1751 .name = "cherryview-pinctrl",
1752 .pm = &chv_pinctrl_pm_ops,
1753 .acpi_match_table = chv_pinctrl_acpi_match,
1754 },
1755 };
1756
1757 static int __init chv_pinctrl_init(void)
1758 {
1759 return platform_driver_register(&chv_pinctrl_driver);
1760 }
1761 subsys_initcall(chv_pinctrl_init);
1762
1763 static void __exit chv_pinctrl_exit(void)
1764 {
1765 platform_driver_unregister(&chv_pinctrl_driver);
1766 }
1767 module_exit(chv_pinctrl_exit);
1768
1769 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1770 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1771 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support