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PM / Domains: Fix a warning message
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-st.c
blob99da4cf91031b49757cc24735057b72c3d4f760e
1 /*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Authors:
4 * Srinivas Kandagatla <srinivas.kandagatla@st.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/slab.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/of.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_gpio.h>
19 #include <linux/of_address.h>
20 #include <linux/regmap.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/platform_device.h>
26 #include "core.h"
27
28 /* PIO Block registers */
29 /* PIO output */
30 #define REG_PIO_POUT 0x00
31 /* Set bits of POUT */
32 #define REG_PIO_SET_POUT 0x04
33 /* Clear bits of POUT */
34 #define REG_PIO_CLR_POUT 0x08
35 /* PIO input */
36 #define REG_PIO_PIN 0x10
37 /* PIO configuration */
38 #define REG_PIO_PC(n) (0x20 + (n) * 0x10)
39 /* Set bits of PC[2:0] */
40 #define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10)
41 /* Clear bits of PC[2:0] */
42 #define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10)
43 /* PIO input comparison */
44 #define REG_PIO_PCOMP 0x50
45 /* Set bits of PCOMP */
46 #define REG_PIO_SET_PCOMP 0x54
47 /* Clear bits of PCOMP */
48 #define REG_PIO_CLR_PCOMP 0x58
49 /* PIO input comparison mask */
50 #define REG_PIO_PMASK 0x60
51 /* Set bits of PMASK */
52 #define REG_PIO_SET_PMASK 0x64
53 /* Clear bits of PMASK */
54 #define REG_PIO_CLR_PMASK 0x68
55
56 #define ST_GPIO_DIRECTION_BIDIR 0x1
57 #define ST_GPIO_DIRECTION_OUT 0x2
58 #define ST_GPIO_DIRECTION_IN 0x4
59
60 /**
61 * Packed style retime configuration.
62 * There are two registers cfg0 and cfg1 in this style for each bank.
63 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
64 */
65 #define RT_P_CFGS_PER_BANK 2
66 #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7)
67 #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23)
68 #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31)
69 #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7)
70 #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15)
71 #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23)
72 #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31)
73
74 /**
75 * Dedicated style retime Configuration register
76 * each register is dedicated per pin.
77 */
78 #define RT_D_CFGS_PER_BANK 8
79 #define RT_D_CFG_CLK_SHIFT 0
80 #define RT_D_CFG_CLK_MASK (0x3 << 0)
81 #define RT_D_CFG_CLKNOTDATA_SHIFT 2
82 #define RT_D_CFG_CLKNOTDATA_MASK BIT(2)
83 #define RT_D_CFG_DELAY_SHIFT 3
84 #define RT_D_CFG_DELAY_MASK (0xf << 3)
85 #define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7
86 #define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7)
87 #define RT_D_CFG_DOUBLE_EDGE_SHIFT 8
88 #define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8)
89 #define RT_D_CFG_INVERTCLK_SHIFT 9
90 #define RT_D_CFG_INVERTCLK_MASK BIT(9)
91 #define RT_D_CFG_RETIME_SHIFT 10
92 #define RT_D_CFG_RETIME_MASK BIT(10)
93
94 /*
95 * Pinconf is represented in an opaque unsigned long variable.
96 * Below is the bit allocation details for each possible configuration.
97 * All the bit fields can be encapsulated into four variables
98 * (direction, retime-type, retime-clk, retime-delay)
99 *
100 * +----------------+
101 *[31:28]| reserved-3 |
102 * +----------------+-------------
103 *[27] | oe | |
104 * +----------------+ v
105 *[26] | pu | [Direction ]
106 * +----------------+ ^
107 *[25] | od | |
108 * +----------------+-------------
109 *[24] | reserved-2 |
110 * +----------------+-------------
111 *[23] | retime | |
112 * +----------------+ |
113 *[22] | retime-invclk | |
114 * +----------------+ v
115 *[21] |retime-clknotdat| [Retime-type ]
116 * +----------------+ ^
117 *[20] | retime-de | |
118 * +----------------+-------------
119 *[19:18]| retime-clk |------>[Retime-Clk ]
120 * +----------------+
121 *[17:16]| reserved-1 |
122 * +----------------+
123 *[15..0]| retime-delay |------>[Retime Delay]
124 * +----------------+
125 */
126
127 #define ST_PINCONF_UNPACK(conf, param)\
128 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \
129 & ST_PINCONF_ ##param ##_MASK)
130
131 #define ST_PINCONF_PACK(conf, val, param) (conf |=\
132 ((val & ST_PINCONF_ ##param ##_MASK) << \
133 ST_PINCONF_ ##param ##_SHIFT))
134
135 /* Output enable */
136 #define ST_PINCONF_OE_MASK 0x1
137 #define ST_PINCONF_OE_SHIFT 27
138 #define ST_PINCONF_OE BIT(27)
139 #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE)
140 #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE)
141
142 /* Pull Up */
143 #define ST_PINCONF_PU_MASK 0x1
144 #define ST_PINCONF_PU_SHIFT 26
145 #define ST_PINCONF_PU BIT(26)
146 #define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU)
147 #define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU)
148
149 /* Open Drain */
150 #define ST_PINCONF_OD_MASK 0x1
151 #define ST_PINCONF_OD_SHIFT 25
152 #define ST_PINCONF_OD BIT(25)
153 #define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD)
154 #define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD)
155
156 #define ST_PINCONF_RT_MASK 0x1
157 #define ST_PINCONF_RT_SHIFT 23
158 #define ST_PINCONF_RT BIT(23)
159 #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT)
160 #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT)
161
162 #define ST_PINCONF_RT_INVERTCLK_MASK 0x1
163 #define ST_PINCONF_RT_INVERTCLK_SHIFT 22
164 #define ST_PINCONF_RT_INVERTCLK BIT(22)
165 #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \
166 ST_PINCONF_UNPACK(conf, RT_INVERTCLK)
167 #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \
168 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)
169
170 #define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1
171 #define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21
172 #define ST_PINCONF_RT_CLKNOTDATA BIT(21)
173 #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \
174 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
175 #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \
176 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)
177
178 #define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1
179 #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20
180 #define ST_PINCONF_RT_DOUBLE_EDGE BIT(20)
181 #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
182 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
183 #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \
184 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)
185
186 #define ST_PINCONF_RT_CLK_MASK 0x3
187 #define ST_PINCONF_RT_CLK_SHIFT 18
188 #define ST_PINCONF_RT_CLK BIT(18)
189 #define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK)
190 #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)
191
192 /* RETIME_DELAY in Pico Secs */
193 #define ST_PINCONF_RT_DELAY_MASK 0xffff
194 #define ST_PINCONF_RT_DELAY_SHIFT 0
195 #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)
196 #define ST_PINCONF_PACK_RT_DELAY(conf, val) \
197 ST_PINCONF_PACK(conf, val, RT_DELAY)
198
199 #define ST_GPIO_PINS_PER_BANK (8)
200 #define OF_GPIO_ARGS_MIN (4)
201 #define OF_RT_ARGS_MIN (2)
202
203 #define gpio_range_to_bank(chip) \
204 container_of(chip, struct st_gpio_bank, range)
205
206 #define pc_to_bank(pc) \
207 container_of(pc, struct st_gpio_bank, pc)
208
209 enum st_retime_style {
210 st_retime_style_none,
211 st_retime_style_packed,
212 st_retime_style_dedicated,
213 };
214
215 struct st_retime_dedicated {
216 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK];
217 };
218
219 struct st_retime_packed {
220 struct regmap_field *clk1notclk0;
221 struct regmap_field *delay_0;
222 struct regmap_field *delay_1;
223 struct regmap_field *invertclk;
224 struct regmap_field *retime;
225 struct regmap_field *clknotdata;
226 struct regmap_field *double_edge;
227 };
228
229 struct st_pio_control {
230 u32 rt_pin_mask;
231 struct regmap_field *alt, *oe, *pu, *od;
232 /* retiming */
233 union {
234 struct st_retime_packed rt_p;
235 struct st_retime_dedicated rt_d;
236 } rt;
237 };
238
239 struct st_pctl_data {
240 const enum st_retime_style rt_style;
241 const unsigned int *input_delays;
242 const int ninput_delays;
243 const unsigned int *output_delays;
244 const int noutput_delays;
245 /* register offset information */
246 const int alt, oe, pu, od, rt;
247 };
248
249 struct st_pinconf {
250 int pin;
251 const char *name;
252 unsigned long config;
253 int altfunc;
254 };
255
256 struct st_pmx_func {
257 const char *name;
258 const char **groups;
259 unsigned ngroups;
260 };
261
262 struct st_pctl_group {
263 const char *name;
264 unsigned int *pins;
265 unsigned npins;
266 struct st_pinconf *pin_conf;
267 };
268
269 /*
270 * Edge triggers are not supported at hardware level, it is supported by
271 * software by exploiting the level trigger support in hardware.
272 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
273 * of each gpio pin in a GPIO bank.
274 *
275 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
276 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
277 *
278 * bit allocation per pin is:
279 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
280 * --------------------------------------------------------
281 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
282 * --------------------------------------------------------
283 *
284 * A pin can have one of following the values in its edge configuration field.
285 *
286 * ------- ----------------------------
287 * [0-3] - Description
288 * ------- ----------------------------
289 * 0000 - No edge IRQ.
290 * 0001 - Falling edge IRQ.
291 * 0010 - Rising edge IRQ.
292 * 0011 - Rising and Falling edge IRQ.
293 * ------- ----------------------------
294 */
295
296 #define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4
297 #define ST_IRQ_EDGE_MASK 0xf
298 #define ST_IRQ_EDGE_FALLING BIT(0)
299 #define ST_IRQ_EDGE_RISING BIT(1)
300 #define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1))
301
302 #define ST_IRQ_RISING_EDGE_CONF(pin) \
303 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
304
305 #define ST_IRQ_FALLING_EDGE_CONF(pin) \
306 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
307
308 #define ST_IRQ_BOTH_EDGE_CONF(pin) \
309 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
310
311 #define ST_IRQ_EDGE_CONF(conf, pin) \
312 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
313
314 struct st_gpio_bank {
315 struct gpio_chip gpio_chip;
316 struct pinctrl_gpio_range range;
317 void __iomem *base;
318 struct st_pio_control pc;
319 unsigned long irq_edge_conf;
320 spinlock_t lock;
321 };
322
323 struct st_pinctrl {
324 struct device *dev;
325 struct pinctrl_dev *pctl;
326 struct st_gpio_bank *banks;
327 int nbanks;
328 struct st_pmx_func *functions;
329 int nfunctions;
330 struct st_pctl_group *groups;
331 int ngroups;
332 struct regmap *regmap;
333 const struct st_pctl_data *data;
334 void __iomem *irqmux_base;
335 };
336
337 /* SOC specific data */
338
339 static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250,
340 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
341
342 static const struct st_pctl_data stih407_data = {
343 .rt_style = st_retime_style_dedicated,
344 .input_delays = stih407_delays,
345 .ninput_delays = ARRAY_SIZE(stih407_delays),
346 .output_delays = stih407_delays,
347 .noutput_delays = ARRAY_SIZE(stih407_delays),
348 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
349 };
350
351 static const struct st_pctl_data stih407_flashdata = {
352 .rt_style = st_retime_style_none,
353 .input_delays = stih407_delays,
354 .ninput_delays = ARRAY_SIZE(stih407_delays),
355 .output_delays = stih407_delays,
356 .noutput_delays = ARRAY_SIZE(stih407_delays),
357 .alt = 0,
358 .oe = -1, /* Not Available */
359 .pu = -1, /* Not Available */
360 .od = 60,
361 .rt = 100,
362 };
363
364 static struct st_pio_control *st_get_pio_control(
365 struct pinctrl_dev *pctldev, int pin)
366 {
367 struct pinctrl_gpio_range *range =
368 pinctrl_find_gpio_range_from_pin(pctldev, pin);
369 struct st_gpio_bank *bank = gpio_range_to_bank(range);
370
371 return &bank->pc;
372 }
373
374 /* Low level functions.. */
375 static inline int st_gpio_bank(int gpio)
376 {
377 return gpio/ST_GPIO_PINS_PER_BANK;
378 }
379
380 static inline int st_gpio_pin(int gpio)
381 {
382 return gpio%ST_GPIO_PINS_PER_BANK;
383 }
384
385 static void st_pinconf_set_config(struct st_pio_control *pc,
386 int pin, unsigned long config)
387 {
388 struct regmap_field *output_enable = pc->oe;
389 struct regmap_field *pull_up = pc->pu;
390 struct regmap_field *open_drain = pc->od;
391 unsigned int oe_value, pu_value, od_value;
392 unsigned long mask = BIT(pin);
393
394 if (output_enable) {
395 regmap_field_read(output_enable, &oe_value);
396 oe_value &= ~mask;
397 if (config & ST_PINCONF_OE)
398 oe_value |= mask;
399 regmap_field_write(output_enable, oe_value);
400 }
401
402 if (pull_up) {
403 regmap_field_read(pull_up, &pu_value);
404 pu_value &= ~mask;
405 if (config & ST_PINCONF_PU)
406 pu_value |= mask;
407 regmap_field_write(pull_up, pu_value);
408 }
409
410 if (open_drain) {
411 regmap_field_read(open_drain, &od_value);
412 od_value &= ~mask;
413 if (config & ST_PINCONF_OD)
414 od_value |= mask;
415 regmap_field_write(open_drain, od_value);
416 }
417 }
418
419 static void st_pctl_set_function(struct st_pio_control *pc,
420 int pin_id, int function)
421 {
422 struct regmap_field *alt = pc->alt;
423 unsigned int val;
424 int pin = st_gpio_pin(pin_id);
425 int offset = pin * 4;
426
427 if (!alt)
428 return;
429
430 regmap_field_read(alt, &val);
431 val &= ~(0xf << offset);
432 val |= function << offset;
433 regmap_field_write(alt, val);
434 }
435
436 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin)
437 {
438 struct regmap_field *alt = pc->alt;
439 unsigned int val;
440 int offset = pin * 4;
441
442 if (!alt)
443 return 0;
444
445 regmap_field_read(alt, &val);
446
447 return (val >> offset) & 0xf;
448 }
449
450 static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
451 const struct st_pctl_data *data, unsigned long config)
452 {
453 const unsigned int *delay_times;
454 int num_delay_times, i, closest_index = -1;
455 unsigned int closest_divergence = UINT_MAX;
456
457 if (ST_PINCONF_UNPACK_OE(config)) {
458 delay_times = data->output_delays;
459 num_delay_times = data->noutput_delays;
460 } else {
461 delay_times = data->input_delays;
462 num_delay_times = data->ninput_delays;
463 }
464
465 for (i = 0; i < num_delay_times; i++) {
466 unsigned int divergence = abs(delay - delay_times[i]);
467
468 if (divergence == 0)
469 return i;
470
471 if (divergence < closest_divergence) {
472 closest_divergence = divergence;
473 closest_index = i;
474 }
475 }
476
477 pr_warn("Attempt to set delay %d, closest available %d\n",
478 delay, delay_times[closest_index]);
479
480 return closest_index;
481 }
482
483 static unsigned long st_pinconf_bit_to_delay(unsigned int index,
484 const struct st_pctl_data *data, unsigned long output)
485 {
486 const unsigned int *delay_times;
487 int num_delay_times;
488
489 if (output) {
490 delay_times = data->output_delays;
491 num_delay_times = data->noutput_delays;
492 } else {
493 delay_times = data->input_delays;
494 num_delay_times = data->ninput_delays;
495 }
496
497 if (index < num_delay_times) {
498 return delay_times[index];
499 } else {
500 pr_warn("Delay not found in/out delay list\n");
501 return 0;
502 }
503 }
504
505 static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field,
506 int enable, int pin)
507 {
508 unsigned int val = 0;
509
510 regmap_field_read(field, &val);
511 if (enable)
512 val |= BIT(pin);
513 else
514 val &= ~BIT(pin);
515 regmap_field_write(field, val);
516 }
517
518 static void st_pinconf_set_retime_packed(struct st_pinctrl *info,
519 struct st_pio_control *pc, unsigned long config, int pin)
520 {
521 const struct st_pctl_data *data = info->data;
522 struct st_retime_packed *rt_p = &pc->rt.rt_p;
523 unsigned int delay;
524
525 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0,
526 ST_PINCONF_UNPACK_RT_CLK(config), pin);
527
528 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata,
529 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin);
530
531 st_regmap_field_bit_set_clear_pin(rt_p->double_edge,
532 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin);
533
534 st_regmap_field_bit_set_clear_pin(rt_p->invertclk,
535 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin);
536
537 st_regmap_field_bit_set_clear_pin(rt_p->retime,
538 ST_PINCONF_UNPACK_RT(config), pin);
539
540 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config),
541 data, config);
542 /* 2 bit delay, lsb */
543 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
544 /* 2 bit delay, msb */
545 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);
546
547 }
548
549 static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,
550 struct st_pio_control *pc, unsigned long config, int pin)
551 {
552 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1;
553 int clk = ST_PINCONF_UNPACK_RT_CLK(config);
554 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config);
555 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
556 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config);
557 int retime = ST_PINCONF_UNPACK_RT(config);
558
559 unsigned long delay = st_pinconf_delay_to_bit(
560 ST_PINCONF_UNPACK_RT_DELAY(config),
561 info->data, config);
562 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
563
564 unsigned long retime_config =
565 ((clk) << RT_D_CFG_CLK_SHIFT) |
566 ((delay) << RT_D_CFG_DELAY_SHIFT) |
567 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) |
568 ((retime) << RT_D_CFG_RETIME_SHIFT) |
569 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) |
570 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) |
571 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT);
572
573 regmap_field_write(rt_d->rt[pin], retime_config);
574 }
575
576 static void st_pinconf_get_direction(struct st_pio_control *pc,
577 int pin, unsigned long *config)
578 {
579 unsigned int oe_value, pu_value, od_value;
580
581 if (pc->oe) {
582 regmap_field_read(pc->oe, &oe_value);
583 if (oe_value & BIT(pin))
584 ST_PINCONF_PACK_OE(*config);
585 }
586
587 if (pc->pu) {
588 regmap_field_read(pc->pu, &pu_value);
589 if (pu_value & BIT(pin))
590 ST_PINCONF_PACK_PU(*config);
591 }
592
593 if (pc->od) {
594 regmap_field_read(pc->od, &od_value);
595 if (od_value & BIT(pin))
596 ST_PINCONF_PACK_OD(*config);
597 }
598 }
599
600 static int st_pinconf_get_retime_packed(struct st_pinctrl *info,
601 struct st_pio_control *pc, int pin, unsigned long *config)
602 {
603 const struct st_pctl_data *data = info->data;
604 struct st_retime_packed *rt_p = &pc->rt.rt_p;
605 unsigned int delay_bits, delay, delay0, delay1, val;
606 int output = ST_PINCONF_UNPACK_OE(*config);
607
608 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin)))
609 ST_PINCONF_PACK_RT(*config);
610
611 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin)))
612 ST_PINCONF_PACK_RT_CLK(*config, 1);
613
614 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin)))
615 ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
616
617 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin)))
618 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
619
620 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin)))
621 ST_PINCONF_PACK_RT_INVERTCLK(*config);
622
623 regmap_field_read(rt_p->delay_0, &delay0);
624 regmap_field_read(rt_p->delay_1, &delay1);
625 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) |
626 (((delay0 & BIT(pin)) ? 1 : 0));
627 delay = st_pinconf_bit_to_delay(delay_bits, data, output);
628 ST_PINCONF_PACK_RT_DELAY(*config, delay);
629
630 return 0;
631 }
632
633 static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info,
634 struct st_pio_control *pc, int pin, unsigned long *config)
635 {
636 unsigned int value;
637 unsigned long delay_bits, delay, rt_clk;
638 int output = ST_PINCONF_UNPACK_OE(*config);
639 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
640
641 regmap_field_read(rt_d->rt[pin], &value);
642
643 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT;
644 ST_PINCONF_PACK_RT_CLK(*config, rt_clk);
645
646 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT;
647 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output);
648 ST_PINCONF_PACK_RT_DELAY(*config, delay);
649
650 if (value & RT_D_CFG_CLKNOTDATA_MASK)
651 ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
652
653 if (value & RT_D_CFG_DOUBLE_EDGE_MASK)
654 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
655
656 if (value & RT_D_CFG_INVERTCLK_MASK)
657 ST_PINCONF_PACK_RT_INVERTCLK(*config);
658
659 if (value & RT_D_CFG_RETIME_MASK)
660 ST_PINCONF_PACK_RT(*config);
661
662 return 0;
663 }
664
665 /* GPIO related functions */
666
667 static inline void __st_gpio_set(struct st_gpio_bank *bank,
668 unsigned offset, int value)
669 {
670 if (value)
671 writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
672 else
673 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
674 }
675
676 static void st_gpio_direction(struct st_gpio_bank *bank,
677 unsigned int gpio, unsigned int direction)
678 {
679 int offset = st_gpio_pin(gpio);
680 int i = 0;
681 /**
682 * There are three configuration registers (PIOn_PC0, PIOn_PC1
683 * and PIOn_PC2) for each port. These are used to configure the
684 * PIO port pins. Each pin can be configured as an input, output,
685 * bidirectional, or alternative function pin. Three bits, one bit
686 * from each of the three registers, configure the corresponding bit of
687 * the port. Valid bit settings is:
688 *
689 * PC2 PC1 PC0 Direction.
690 * 0 0 0 [Input Weak pull-up]
691 * 0 0 or 1 1 [Bidirection]
692 * 0 1 0 [Output]
693 * 1 0 0 [Input]
694 *
695 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits
696 * individually.
697 */
698 for (i = 0; i <= 2; i++) {
699 if (direction & BIT(i))
700 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
701 else
702 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
703 }
704 }
705
706 static int st_gpio_get(struct gpio_chip *chip, unsigned offset)
707 {
708 struct st_gpio_bank *bank = gpiochip_get_data(chip);
709
710 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
711 }
712
713 static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
714 {
715 struct st_gpio_bank *bank = gpiochip_get_data(chip);
716 __st_gpio_set(bank, offset, value);
717 }
718
719 static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
720 {
721 pinctrl_gpio_direction_input(chip->base + offset);
722
723 return 0;
724 }
725
726 static int st_gpio_direction_output(struct gpio_chip *chip,
727 unsigned offset, int value)
728 {
729 struct st_gpio_bank *bank = gpiochip_get_data(chip);
730
731 __st_gpio_set(bank, offset, value);
732 pinctrl_gpio_direction_output(chip->base + offset);
733
734 return 0;
735 }
736
737 static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
738 {
739 struct st_gpio_bank *bank = gpiochip_get_data(chip);
740 struct st_pio_control pc = bank->pc;
741 unsigned long config;
742 unsigned int direction = 0;
743 unsigned int function;
744 unsigned int value;
745 int i = 0;
746
747 /* Alternate function direction is handled by Pinctrl */
748 function = st_pctl_get_pin_function(&pc, offset);
749 if (function) {
750 st_pinconf_get_direction(&pc, offset, &config);
751 return !ST_PINCONF_UNPACK_OE(config);
752 }
753
754 /*
755 * GPIO direction is handled differently
756 * - See st_gpio_direction() above for an explanation
757 */
758 for (i = 0; i <= 2; i++) {
759 value = readl(bank->base + REG_PIO_PC(i));
760 direction |= ((value >> offset) & 0x1) << i;
761 }
762
763 return (direction == ST_GPIO_DIRECTION_IN);
764 }
765
766 /* Pinctrl Groups */
767 static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev)
768 {
769 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
770
771 return info->ngroups;
772 }
773
774 static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev,
775 unsigned selector)
776 {
777 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
778
779 return info->groups[selector].name;
780 }
781
782 static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,
783 unsigned selector, const unsigned **pins, unsigned *npins)
784 {
785 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
786
787 if (selector >= info->ngroups)
788 return -EINVAL;
789
790 *pins = info->groups[selector].pins;
791 *npins = info->groups[selector].npins;
792
793 return 0;
794 }
795
796 static inline const struct st_pctl_group *st_pctl_find_group_by_name(
797 const struct st_pinctrl *info, const char *name)
798 {
799 int i;
800
801 for (i = 0; i < info->ngroups; i++) {
802 if (!strcmp(info->groups[i].name, name))
803 return &info->groups[i];
804 }
805
806 return NULL;
807 }
808
809 static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
810 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
811 {
812 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
813 const struct st_pctl_group *grp;
814 struct pinctrl_map *new_map;
815 struct device_node *parent;
816 int map_num, i;
817
818 grp = st_pctl_find_group_by_name(info, np->name);
819 if (!grp) {
820 dev_err(info->dev, "unable to find group for node %s\n",
821 np->name);
822 return -EINVAL;
823 }
824
825 map_num = grp->npins + 1;
826 new_map = devm_kzalloc(pctldev->dev,
827 sizeof(*new_map) * map_num, GFP_KERNEL);
828 if (!new_map)
829 return -ENOMEM;
830
831 parent = of_get_parent(np);
832 if (!parent) {
833 devm_kfree(pctldev->dev, new_map);
834 return -EINVAL;
835 }
836
837 *map = new_map;
838 *num_maps = map_num;
839 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
840 new_map[0].data.mux.function = parent->name;
841 new_map[0].data.mux.group = np->name;
842 of_node_put(parent);
843
844 /* create config map per pin */
845 new_map++;
846 for (i = 0; i < grp->npins; i++) {
847 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
848 new_map[i].data.configs.group_or_pin =
849 pin_get_name(pctldev, grp->pins[i]);
850 new_map[i].data.configs.configs = &grp->pin_conf[i].config;
851 new_map[i].data.configs.num_configs = 1;
852 }
853 dev_info(pctldev->dev, "maps: function %s group %s num %d\n",
854 (*map)->data.mux.function, grp->name, map_num);
855
856 return 0;
857 }
858
859 static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,
860 struct pinctrl_map *map, unsigned num_maps)
861 {
862 }
863
864 static struct pinctrl_ops st_pctlops = {
865 .get_groups_count = st_pctl_get_groups_count,
866 .get_group_pins = st_pctl_get_group_pins,
867 .get_group_name = st_pctl_get_group_name,
868 .dt_node_to_map = st_pctl_dt_node_to_map,
869 .dt_free_map = st_pctl_dt_free_map,
870 };
871
872 /* Pinmux */
873 static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
874 {
875 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
876
877 return info->nfunctions;
878 }
879
880 static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
881 unsigned selector)
882 {
883 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
884
885 return info->functions[selector].name;
886 }
887
888 static int st_pmx_get_groups(struct pinctrl_dev *pctldev,
889 unsigned selector, const char * const **grps, unsigned * const ngrps)
890 {
891 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
892 *grps = info->functions[selector].groups;
893 *ngrps = info->functions[selector].ngroups;
894
895 return 0;
896 }
897
898 static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
899 unsigned group)
900 {
901 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
902 struct st_pinconf *conf = info->groups[group].pin_conf;
903 struct st_pio_control *pc;
904 int i;
905
906 for (i = 0; i < info->groups[group].npins; i++) {
907 pc = st_get_pio_control(pctldev, conf[i].pin);
908 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc);
909 }
910
911 return 0;
912 }
913
914 static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
915 struct pinctrl_gpio_range *range, unsigned gpio,
916 bool input)
917 {
918 struct st_gpio_bank *bank = gpio_range_to_bank(range);
919 /*
920 * When a PIO bank is used in its primary function mode (altfunc = 0)
921 * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
922 * for the primary PIO functions are driven by the related PIO block
923 */
924 st_pctl_set_function(&bank->pc, gpio, 0);
925 st_gpio_direction(bank, gpio, input ?
926 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT);
927
928 return 0;
929 }
930
931 static struct pinmux_ops st_pmxops = {
932 .get_functions_count = st_pmx_get_funcs_count,
933 .get_function_name = st_pmx_get_fname,
934 .get_function_groups = st_pmx_get_groups,
935 .set_mux = st_pmx_set_mux,
936 .gpio_set_direction = st_pmx_set_gpio_direction,
937 .strict = true,
938 };
939
940 /* Pinconf */
941 static void st_pinconf_get_retime(struct st_pinctrl *info,
942 struct st_pio_control *pc, int pin, unsigned long *config)
943 {
944 if (info->data->rt_style == st_retime_style_packed)
945 st_pinconf_get_retime_packed(info, pc, pin, config);
946 else if (info->data->rt_style == st_retime_style_dedicated)
947 if ((BIT(pin) & pc->rt_pin_mask))
948 st_pinconf_get_retime_dedicated(info, pc,
949 pin, config);
950 }
951
952 static void st_pinconf_set_retime(struct st_pinctrl *info,
953 struct st_pio_control *pc, int pin, unsigned long config)
954 {
955 if (info->data->rt_style == st_retime_style_packed)
956 st_pinconf_set_retime_packed(info, pc, config, pin);
957 else if (info->data->rt_style == st_retime_style_dedicated)
958 if ((BIT(pin) & pc->rt_pin_mask))
959 st_pinconf_set_retime_dedicated(info, pc,
960 config, pin);
961 }
962
963 static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,
964 unsigned long *configs, unsigned num_configs)
965 {
966 int pin = st_gpio_pin(pin_id);
967 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
968 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
969 int i;
970
971 for (i = 0; i < num_configs; i++) {
972 st_pinconf_set_config(pc, pin, configs[i]);
973 st_pinconf_set_retime(info, pc, pin, configs[i]);
974 } /* for each config */
975
976 return 0;
977 }
978
979 static int st_pinconf_get(struct pinctrl_dev *pctldev,
980 unsigned pin_id, unsigned long *config)
981 {
982 int pin = st_gpio_pin(pin_id);
983 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
984 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
985
986 *config = 0;
987 st_pinconf_get_direction(pc, pin, config);
988 st_pinconf_get_retime(info, pc, pin, config);
989
990 return 0;
991 }
992
993 static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
994 struct seq_file *s, unsigned pin_id)
995 {
996 struct st_pio_control *pc;
997 unsigned long config;
998 unsigned int function;
999 int offset = st_gpio_pin(pin_id);
1000 char f[16];
1001
1002 mutex_unlock(&pctldev->mutex);
1003 pc = st_get_pio_control(pctldev, pin_id);
1004 st_pinconf_get(pctldev, pin_id, &config);
1005 mutex_lock(&pctldev->mutex);
1006
1007 function = st_pctl_get_pin_function(pc, offset);
1008 if (function)
1009 snprintf(f, 10, "Alt Fn %d", function);
1010 else
1011 snprintf(f, 5, "GPIO");
1012
1013 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n"
1014 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
1015 "de:%ld,rt-clk:%ld,rt-delay:%ld]",
1016 !st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset),
1017 ST_PINCONF_UNPACK_PU(config),
1018 ST_PINCONF_UNPACK_OD(config),
1019 f,
1020 ST_PINCONF_UNPACK_RT(config),
1021 ST_PINCONF_UNPACK_RT_INVERTCLK(config),
1022 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config),
1023 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
1024 ST_PINCONF_UNPACK_RT_CLK(config),
1025 ST_PINCONF_UNPACK_RT_DELAY(config));
1026 }
1027
1028 static struct pinconf_ops st_confops = {
1029 .pin_config_get = st_pinconf_get,
1030 .pin_config_set = st_pinconf_set,
1031 .pin_config_dbg_show = st_pinconf_dbg_show,
1032 };
1033
1034 static void st_pctl_dt_child_count(struct st_pinctrl *info,
1035 struct device_node *np)
1036 {
1037 struct device_node *child;
1038 for_each_child_of_node(np, child) {
1039 if (of_property_read_bool(child, "gpio-controller")) {
1040 info->nbanks++;
1041 } else {
1042 info->nfunctions++;
1043 info->ngroups += of_get_child_count(child);
1044 }
1045 }
1046 }
1047
1048 static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info,
1049 int bank, struct st_pio_control *pc)
1050 {
1051 struct device *dev = info->dev;
1052 struct regmap *rm = info->regmap;
1053 const struct st_pctl_data *data = info->data;
1054 /* 2 registers per bank */
1055 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;
1056 struct st_retime_packed *rt_p = &pc->rt.rt_p;
1057 /* cfg0 */
1058 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg);
1059 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg);
1060 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg);
1061 /* cfg1 */
1062 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4);
1063 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4);
1064 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4);
1065 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4);
1066
1067 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0);
1068 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0);
1069 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1);
1070 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk);
1071 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime);
1072 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata);
1073 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge);
1074
1075 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) ||
1076 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) ||
1077 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) ||
1078 IS_ERR(rt_p->double_edge))
1079 return -EINVAL;
1080
1081 return 0;
1082 }
1083
1084 static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info,
1085 int bank, struct st_pio_control *pc)
1086 {
1087 struct device *dev = info->dev;
1088 struct regmap *rm = info->regmap;
1089 const struct st_pctl_data *data = info->data;
1090 /* 8 registers per bank */
1091 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;
1092 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
1093 unsigned int j;
1094 u32 pin_mask = pc->rt_pin_mask;
1095
1096 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) {
1097 if (BIT(j) & pin_mask) {
1098 struct reg_field reg = REG_FIELD(reg_offset, 0, 31);
1099 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg);
1100 if (IS_ERR(rt_d->rt[j]))
1101 return -EINVAL;
1102 reg_offset += 4;
1103 }
1104 }
1105 return 0;
1106 }
1107
1108 static int st_pctl_dt_setup_retime(struct st_pinctrl *info,
1109 int bank, struct st_pio_control *pc)
1110 {
1111 const struct st_pctl_data *data = info->data;
1112 if (data->rt_style == st_retime_style_packed)
1113 return st_pctl_dt_setup_retime_packed(info, bank, pc);
1114 else if (data->rt_style == st_retime_style_dedicated)
1115 return st_pctl_dt_setup_retime_dedicated(info, bank, pc);
1116
1117 return -EINVAL;
1118 }
1119
1120
1121 static struct regmap_field *st_pc_get_value(struct device *dev,
1122 struct regmap *regmap, int bank,
1123 int data, int lsb, int msb)
1124 {
1125 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);
1126
1127 if (data < 0)
1128 return NULL;
1129
1130 return devm_regmap_field_alloc(dev, regmap, reg);
1131 }
1132
1133 static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
1134 struct device_node *np)
1135 {
1136 const struct st_pctl_data *data = info->data;
1137 /**
1138 * For a given shared register like OE/PU/OD, there are 8 bits per bank
1139 * 0:7 belongs to bank0, 8:15 belongs to bank1 ...
1140 * So each register is shared across 4 banks.
1141 */
1142 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;
1143 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1;
1144 struct st_pio_control *pc = &info->banks[bank].pc;
1145 struct device *dev = info->dev;
1146 struct regmap *regmap = info->regmap;
1147
1148 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);
1149 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);
1150 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
1151 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
1152
1153 /* retime avaiable for all pins by default */
1154 pc->rt_pin_mask = 0xff;
1155 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);
1156 st_pctl_dt_setup_retime(info, bank, pc);
1157
1158 return;
1159 }
1160
1161 /*
1162 * Each pin is represented in of the below forms.
1163 * <bank offset mux direction rt_type rt_delay rt_clk>
1164 */
1165 static int st_pctl_dt_parse_groups(struct device_node *np,
1166 struct st_pctl_group *grp, struct st_pinctrl *info, int idx)
1167 {
1168 /* bank pad direction val altfunction */
1169 const __be32 *list;
1170 struct property *pp;
1171 struct st_pinconf *conf;
1172 struct device_node *pins;
1173 int i = 0, npins = 0, nr_props;
1174
1175 pins = of_get_child_by_name(np, "st,pins");
1176 if (!pins)
1177 return -ENODATA;
1178
1179 for_each_property_of_node(pins, pp) {
1180 /* Skip those we do not want to proceed */
1181 if (!strcmp(pp->name, "name"))
1182 continue;
1183
1184 if (pp && (pp->length/sizeof(__be32)) >= OF_GPIO_ARGS_MIN) {
1185 npins++;
1186 } else {
1187 pr_warn("Invalid st,pins in %s node\n", np->name);
1188 return -EINVAL;
1189 }
1190 }
1191
1192 grp->npins = npins;
1193 grp->name = np->name;
1194 grp->pins = devm_kzalloc(info->dev, npins * sizeof(u32), GFP_KERNEL);
1195 grp->pin_conf = devm_kzalloc(info->dev,
1196 npins * sizeof(*conf), GFP_KERNEL);
1197
1198 if (!grp->pins || !grp->pin_conf)
1199 return -ENOMEM;
1200
1201 /* <bank offset mux direction rt_type rt_delay rt_clk> */
1202 for_each_property_of_node(pins, pp) {
1203 if (!strcmp(pp->name, "name"))
1204 continue;
1205 nr_props = pp->length/sizeof(u32);
1206 list = pp->value;
1207 conf = &grp->pin_conf[i];
1208
1209 /* bank & offset */
1210 be32_to_cpup(list++);
1211 be32_to_cpup(list++);
1212 conf->pin = of_get_named_gpio(pins, pp->name, 0);
1213 conf->name = pp->name;
1214 grp->pins[i] = conf->pin;
1215 /* mux */
1216 conf->altfunc = be32_to_cpup(list++);
1217 conf->config = 0;
1218 /* direction */
1219 conf->config |= be32_to_cpup(list++);
1220 /* rt_type rt_delay rt_clk */
1221 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) {
1222 /* rt_type */
1223 conf->config |= be32_to_cpup(list++);
1224 /* rt_delay */
1225 conf->config |= be32_to_cpup(list++);
1226 /* rt_clk */
1227 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN)
1228 conf->config |= be32_to_cpup(list++);
1229 }
1230 i++;
1231 }
1232 of_node_put(pins);
1233
1234 return 0;
1235 }
1236
1237 static int st_pctl_parse_functions(struct device_node *np,
1238 struct st_pinctrl *info, u32 index, int *grp_index)
1239 {
1240 struct device_node *child;
1241 struct st_pmx_func *func;
1242 struct st_pctl_group *grp;
1243 int ret, i;
1244
1245 func = &info->functions[index];
1246 func->name = np->name;
1247 func->ngroups = of_get_child_count(np);
1248 if (func->ngroups == 0) {
1249 dev_err(info->dev, "No groups defined\n");
1250 return -EINVAL;
1251 }
1252 func->groups = devm_kzalloc(info->dev,
1253 func->ngroups * sizeof(char *), GFP_KERNEL);
1254 if (!func->groups)
1255 return -ENOMEM;
1256
1257 i = 0;
1258 for_each_child_of_node(np, child) {
1259 func->groups[i] = child->name;
1260 grp = &info->groups[*grp_index];
1261 *grp_index += 1;
1262 ret = st_pctl_dt_parse_groups(child, grp, info, i++);
1263 if (ret)
1264 return ret;
1265 }
1266 dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n",
1267 index, func->name, func->ngroups);
1268
1269 return 0;
1270 }
1271
1272 static void st_gpio_irq_mask(struct irq_data *d)
1273 {
1274 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1275 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1276
1277 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);
1278 }
1279
1280 static void st_gpio_irq_unmask(struct irq_data *d)
1281 {
1282 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1283 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1284
1285 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
1286 }
1287
1288 static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
1289 {
1290 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1291 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1292 unsigned long flags;
1293 int comp, pin = d->hwirq;
1294 u32 val;
1295 u32 pin_edge_conf = 0;
1296
1297 switch (type) {
1298 case IRQ_TYPE_LEVEL_HIGH:
1299 comp = 0;
1300 break;
1301 case IRQ_TYPE_EDGE_FALLING:
1302 comp = 0;
1303 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);
1304 break;
1305 case IRQ_TYPE_LEVEL_LOW:
1306 comp = 1;
1307 break;
1308 case IRQ_TYPE_EDGE_RISING:
1309 comp = 1;
1310 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);
1311 break;
1312 case IRQ_TYPE_EDGE_BOTH:
1313 comp = st_gpio_get(&bank->gpio_chip, pin);
1314 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);
1315 break;
1316 default:
1317 return -EINVAL;
1318 }
1319
1320 spin_lock_irqsave(&bank->lock, flags);
1321 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (
1322 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));
1323 bank->irq_edge_conf |= pin_edge_conf;
1324 spin_unlock_irqrestore(&bank->lock, flags);
1325
1326 val = readl(bank->base + REG_PIO_PCOMP);
1327 val &= ~BIT(pin);
1328 val |= (comp << pin);
1329 writel(val, bank->base + REG_PIO_PCOMP);
1330
1331 return 0;
1332 }
1333
1334 /*
1335 * As edge triggers are not supported at hardware level, it is supported by
1336 * software by exploiting the level trigger support in hardware.
1337 *
1338 * Steps for detection raising edge interrupt in software.
1339 *
1340 * Step 1: CONFIGURE pin to detect level LOW interrupts.
1341 *
1342 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
1343 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
1344 * IGNORE calling the actual interrupt handler for the pin at this stage.
1345 *
1346 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1347 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
1348 * DISPATCH the interrupt to the interrupt handler of the pin.
1349 *
1350 * step-1 ________ __________
1351 * | | step - 3
1352 * | |
1353 * step -2 |_____|
1354 *
1355 * falling edge is also detected int the same way.
1356 *
1357 */
1358 static void __gpio_irq_handler(struct st_gpio_bank *bank)
1359 {
1360 unsigned long port_in, port_mask, port_comp, active_irqs;
1361 unsigned long bank_edge_mask, flags;
1362 int n, val, ecfg;
1363
1364 spin_lock_irqsave(&bank->lock, flags);
1365 bank_edge_mask = bank->irq_edge_conf;
1366 spin_unlock_irqrestore(&bank->lock, flags);
1367
1368 for (;;) {
1369 port_in = readl(bank->base + REG_PIO_PIN);
1370 port_comp = readl(bank->base + REG_PIO_PCOMP);
1371 port_mask = readl(bank->base + REG_PIO_PMASK);
1372
1373 active_irqs = (port_in ^ port_comp) & port_mask;
1374
1375 if (active_irqs == 0)
1376 break;
1377
1378 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
1379 /* check if we are detecting fake edges ... */
1380 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);
1381
1382 if (ecfg) {
1383 /* edge detection. */
1384 val = st_gpio_get(&bank->gpio_chip, n);
1385
1386 writel(BIT(n),
1387 val ? bank->base + REG_PIO_SET_PCOMP :
1388 bank->base + REG_PIO_CLR_PCOMP);
1389
1390 if (ecfg != ST_IRQ_EDGE_BOTH &&
1391 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val))
1392 continue;
1393 }
1394
1395 generic_handle_irq(irq_find_mapping(bank->gpio_chip.irqdomain, n));
1396 }
1397 }
1398 }
1399
1400 static void st_gpio_irq_handler(struct irq_desc *desc)
1401 {
1402 /* interrupt dedicated per bank */
1403 struct irq_chip *chip = irq_desc_get_chip(desc);
1404 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1405 struct st_gpio_bank *bank = gpiochip_get_data(gc);
1406
1407 chained_irq_enter(chip, desc);
1408 __gpio_irq_handler(bank);
1409 chained_irq_exit(chip, desc);
1410 }
1411
1412 static void st_gpio_irqmux_handler(struct irq_desc *desc)
1413 {
1414 struct irq_chip *chip = irq_desc_get_chip(desc);
1415 struct st_pinctrl *info = irq_desc_get_handler_data(desc);
1416 unsigned long status;
1417 int n;
1418
1419 chained_irq_enter(chip, desc);
1420
1421 status = readl(info->irqmux_base);
1422
1423 for_each_set_bit(n, &status, info->nbanks)
1424 __gpio_irq_handler(&info->banks[n]);
1425
1426 chained_irq_exit(chip, desc);
1427 }
1428
1429 static struct gpio_chip st_gpio_template = {
1430 .request = gpiochip_generic_request,
1431 .free = gpiochip_generic_free,
1432 .get = st_gpio_get,
1433 .set = st_gpio_set,
1434 .direction_input = st_gpio_direction_input,
1435 .direction_output = st_gpio_direction_output,
1436 .get_direction = st_gpio_get_direction,
1437 .ngpio = ST_GPIO_PINS_PER_BANK,
1438 };
1439
1440 static struct irq_chip st_gpio_irqchip = {
1441 .name = "GPIO",
1442 .irq_disable = st_gpio_irq_mask,
1443 .irq_mask = st_gpio_irq_mask,
1444 .irq_unmask = st_gpio_irq_unmask,
1445 .irq_set_type = st_gpio_irq_set_type,
1446 .flags = IRQCHIP_SKIP_SET_WAKE,
1447 };
1448
1449 static int st_gpiolib_register_bank(struct st_pinctrl *info,
1450 int bank_nr, struct device_node *np)
1451 {
1452 struct st_gpio_bank *bank = &info->banks[bank_nr];
1453 struct pinctrl_gpio_range *range = &bank->range;
1454 struct device *dev = info->dev;
1455 int bank_num = of_alias_get_id(np, "gpio");
1456 struct resource res, irq_res;
1457 int gpio_irq = 0, err;
1458
1459 if (of_address_to_resource(np, 0, &res))
1460 return -ENODEV;
1461
1462 bank->base = devm_ioremap_resource(dev, &res);
1463 if (IS_ERR(bank->base))
1464 return PTR_ERR(bank->base);
1465
1466 bank->gpio_chip = st_gpio_template;
1467 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
1468 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
1469 bank->gpio_chip.of_node = np;
1470 bank->gpio_chip.parent = dev;
1471 spin_lock_init(&bank->lock);
1472
1473 of_property_read_string(np, "st,bank-name", &range->name);
1474 bank->gpio_chip.label = range->name;
1475
1476 range->id = bank_num;
1477 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;
1478 range->npins = bank->gpio_chip.ngpio;
1479 range->gc = &bank->gpio_chip;
1480 err = gpiochip_add_data(&bank->gpio_chip, bank);
1481 if (err) {
1482 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num);
1483 return err;
1484 }
1485 dev_info(dev, "%s bank added.\n", range->name);
1486
1487 /**
1488 * GPIO bank can have one of the two possible types of
1489 * interrupt-wirings.
1490 *
1491 * First type is via irqmux, single interrupt is used by multiple
1492 * gpio banks. This reduces number of overall interrupts numbers
1493 * required. All these banks belong to a single pincontroller.
1494 * _________
1495 * | |----> [gpio-bank (n) ]
1496 * | |----> [gpio-bank (n + 1)]
1497 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
1498 * | |----> [gpio-bank (... )]
1499 * |_________|----> [gpio-bank (n + 7)]
1500 *
1501 * Second type has a dedicated interrupt per each gpio bank.
1502 *
1503 * [irqN]----> [gpio-bank (n)]
1504 */
1505
1506 if (of_irq_to_resource(np, 0, &irq_res)) {
1507 gpio_irq = irq_res.start;
1508 gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip,
1509 gpio_irq, st_gpio_irq_handler);
1510 }
1511
1512 if (info->irqmux_base || gpio_irq > 0) {
1513 err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip,
1514 0, handle_simple_irq,
1515 IRQ_TYPE_LEVEL_LOW);
1516 if (err) {
1517 gpiochip_remove(&bank->gpio_chip);
1518 dev_info(dev, "could not add irqchip\n");
1519 return err;
1520 }
1521 } else {
1522 dev_info(dev, "No IRQ support for %s bank\n", np->full_name);
1523 }
1524
1525 return 0;
1526 }
1527
1528 static const struct of_device_id st_pctl_of_match[] = {
1529 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
1530 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
1531 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
1532 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
1533 { /* sentinel */ }
1534 };
1535
1536 static int st_pctl_probe_dt(struct platform_device *pdev,
1537 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info)
1538 {
1539 int ret = 0;
1540 int i = 0, j = 0, k = 0, bank;
1541 struct pinctrl_pin_desc *pdesc;
1542 struct device_node *np = pdev->dev.of_node;
1543 struct device_node *child;
1544 int grp_index = 0;
1545 int irq = 0;
1546 struct resource *res;
1547
1548 st_pctl_dt_child_count(info, np);
1549 if (!info->nbanks) {
1550 dev_err(&pdev->dev, "you need atleast one gpio bank\n");
1551 return -EINVAL;
1552 }
1553
1554 dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks);
1555 dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1556 dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups);
1557
1558 info->functions = devm_kzalloc(&pdev->dev,
1559 info->nfunctions * sizeof(*info->functions), GFP_KERNEL);
1560
1561 info->groups = devm_kzalloc(&pdev->dev,
1562 info->ngroups * sizeof(*info->groups) , GFP_KERNEL);
1563
1564 info->banks = devm_kzalloc(&pdev->dev,
1565 info->nbanks * sizeof(*info->banks), GFP_KERNEL);
1566
1567 if (!info->functions || !info->groups || !info->banks)
1568 return -ENOMEM;
1569
1570 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1571 if (IS_ERR(info->regmap)) {
1572 dev_err(info->dev, "No syscfg phandle specified\n");
1573 return PTR_ERR(info->regmap);
1574 }
1575 info->data = of_match_node(st_pctl_of_match, np)->data;
1576
1577 irq = platform_get_irq(pdev, 0);
1578
1579 if (irq > 0) {
1580 res = platform_get_resource_byname(pdev,
1581 IORESOURCE_MEM, "irqmux");
1582 info->irqmux_base = devm_ioremap_resource(&pdev->dev, res);
1583
1584 if (IS_ERR(info->irqmux_base))
1585 return PTR_ERR(info->irqmux_base);
1586
1587 irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler,
1588 info);
1589
1590 }
1591
1592 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
1593 pdesc = devm_kzalloc(&pdev->dev,
1594 sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL);
1595 if (!pdesc)
1596 return -ENOMEM;
1597
1598 pctl_desc->pins = pdesc;
1599
1600 bank = 0;
1601 for_each_child_of_node(np, child) {
1602 if (of_property_read_bool(child, "gpio-controller")) {
1603 const char *bank_name = NULL;
1604 ret = st_gpiolib_register_bank(info, bank, child);
1605 if (ret)
1606 return ret;
1607
1608 k = info->banks[bank].range.pin_base;
1609 bank_name = info->banks[bank].range.name;
1610 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
1611 pdesc->number = k;
1612 pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]",
1613 bank_name, j);
1614 pdesc++;
1615 }
1616 st_parse_syscfgs(info, bank, child);
1617 bank++;
1618 } else {
1619 ret = st_pctl_parse_functions(child, info,
1620 i++, &grp_index);
1621 if (ret) {
1622 dev_err(&pdev->dev, "No functions found.\n");
1623 return ret;
1624 }
1625 }
1626 }
1627
1628 return 0;
1629 }
1630
1631 static int st_pctl_probe(struct platform_device *pdev)
1632 {
1633 struct st_pinctrl *info;
1634 struct pinctrl_desc *pctl_desc;
1635 int ret, i;
1636
1637 if (!pdev->dev.of_node) {
1638 dev_err(&pdev->dev, "device node not found.\n");
1639 return -EINVAL;
1640 }
1641
1642 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
1643 if (!pctl_desc)
1644 return -ENOMEM;
1645
1646 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1647 if (!info)
1648 return -ENOMEM;
1649
1650 info->dev = &pdev->dev;
1651 platform_set_drvdata(pdev, info);
1652 ret = st_pctl_probe_dt(pdev, pctl_desc, info);
1653 if (ret)
1654 return ret;
1655
1656 pctl_desc->owner = THIS_MODULE;
1657 pctl_desc->pctlops = &st_pctlops;
1658 pctl_desc->pmxops = &st_pmxops;
1659 pctl_desc->confops = &st_confops;
1660 pctl_desc->name = dev_name(&pdev->dev);
1661
1662 info->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, info);
1663 if (IS_ERR(info->pctl)) {
1664 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1665 return PTR_ERR(info->pctl);
1666 }
1667
1668 for (i = 0; i < info->nbanks; i++)
1669 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range);
1670
1671 return 0;
1672 }
1673
1674 static struct platform_driver st_pctl_driver = {
1675 .driver = {
1676 .name = "st-pinctrl",
1677 .of_match_table = st_pctl_of_match,
1678 },
1679 .probe = st_pctl_probe,
1680 };
1681
1682 static int __init st_pctl_init(void)
1683 {
1684 return platform_driver_register(&st_pctl_driver);
1685 }
1686 arch_initcall(st_pctl_init);
Linux with added FPC-III support