arch/mips/kernel/i8253.c

   1 /*
   2  * i8253.c  8253/PIT functions
   3  *
   4  */
   5 #include <linux/clockchips.h>
   6 #include <linux/init.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/jiffies.h>
   9 #include <linux/module.h>
  10 #include <linux/spinlock.h>
  11
  12 #include <asm/delay.h>
  13 #include <asm/i8253.h>
  14 #include <asm/io.h>
  15 #include <asm/time.h>
  16
  17 DEFINE_SPINLOCK(i8253_lock);
  18
  19 /*
  20  * Initialize the PIT timer.
  21  *
  22  * This is also called after resume to bring the PIT into operation again.
  23  */
  24 static void init_pit_timer(enum clock_event_mode mode,
  25                            struct clock_event_device *evt)
  26 {
  27         unsigned long flags;
  28
  29         spin_lock_irqsave(&i8253_lock, flags);
  30
  31         switch(mode) {
  32         case CLOCK_EVT_MODE_PERIODIC:
  33                 /* binary, mode 2, LSB/MSB, ch 0 */
  34                 outb_p(0x34, PIT_MODE);
  35                 outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
  36                 outb(LATCH >> 8 , PIT_CH0);     /* MSB */
  37                 break;
  38
  39         case CLOCK_EVT_MODE_SHUTDOWN:
  40         case CLOCK_EVT_MODE_UNUSED:
  41                 if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
  42                     evt->mode == CLOCK_EVT_MODE_ONESHOT) {
  43                         outb_p(0x30, PIT_MODE);
  44                         outb_p(0, PIT_CH0);
  45                         outb_p(0, PIT_CH0);
  46                 }
  47                 break;
  48
  49         case CLOCK_EVT_MODE_ONESHOT:
  50                 /* One shot setup */
  51                 outb_p(0x38, PIT_MODE);
  52                 break;
  53
  54         case CLOCK_EVT_MODE_RESUME:
  55                 /* Nothing to do here */
  56                 break;
  57         }
  58         spin_unlock_irqrestore(&i8253_lock, flags);
  59 }
  60
  61 /*
  62  * Program the next event in oneshot mode
  63  *
  64  * Delta is given in PIT ticks
  65  */
  66 static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
  67 {
  68         unsigned long flags;
  69
  70         spin_lock_irqsave(&i8253_lock, flags);
  71         outb_p(delta & 0xff , PIT_CH0); /* LSB */
  72         outb(delta >> 8 , PIT_CH0);     /* MSB */
  73         spin_unlock_irqrestore(&i8253_lock, flags);
  74
  75         return 0;
  76 }
  77
  78 /*
  79  * On UP the PIT can serve all of the possible timer functions. On SMP systems
  80  * it can be solely used for the global tick.
  81  *
  82  * The profiling and update capabilites are switched off once the local apic is
  83  * registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
  84  * !using_apic_timer decisions in do_timer_interrupt_hook()
  85  */
  86 struct clock_event_device pit_clockevent = {
  87         .name           = "pit",
  88         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  89         .set_mode       = init_pit_timer,
  90         .set_next_event = pit_next_event,
  91         .irq            = 0,
  92 };
  93
  94 static irqreturn_t timer_interrupt(int irq, void *dev_id)
  95 {
  96         pit_clockevent.event_handler(&pit_clockevent);
  97
  98         return IRQ_HANDLED;
  99 }
 100
 101 static struct irqaction irq0  = {
 102         .handler = timer_interrupt,
 103         .flags = IRQF_DISABLED | IRQF_NOBALANCING,
 104         .mask = CPU_MASK_NONE,
 105         .name = "timer"
 106 };
 107
 108 /*
 109  * Initialize the conversion factor and the min/max deltas of the clock event
 110  * structure and register the clock event source with the framework.
 111  */
 112 void __init setup_pit_timer(void)
 113 {
 114         struct clock_event_device *cd = &pit_clockevent;
 115         unsigned int cpu = smp_processor_id();
 116
 117         /*
 118          * Start pit with the boot cpu mask and make it global after the
 119          * IO_APIC has been initialized.
 120          */
 121         cd->cpumask = cpumask_of_cpu(cpu);
 122         clockevent_set_clock(cd, CLOCK_TICK_RATE);
 123         cd->max_delta_ns = clockevent_delta2ns(0x7FFF, cd);
 124         cd->min_delta_ns = clockevent_delta2ns(0xF, cd);
 125         clockevents_register_device(cd);
 126
 127         irq0.mask = cpumask_of_cpu(cpu);
 128         setup_irq(0, &irq0);
 129 }
 130
 131 /*
 132  * Since the PIT overflows every tick, its not very useful
 133  * to just read by itself. So use jiffies to emulate a free
 134  * running counter:
 135  */
 136 static cycle_t pit_read(void)
 137 {
 138         unsigned long flags;
 139         int count;
 140         u32 jifs;
 141         static int old_count;
 142         static u32 old_jifs;
 143
 144         spin_lock_irqsave(&i8253_lock, flags);
 145         /*
 146          * Although our caller may have the read side of xtime_lock,
 147          * this is now a seqlock, and we are cheating in this routine
 148          * by having side effects on state that we cannot undo if
 149          * there is a collision on the seqlock and our caller has to
 150          * retry.  (Namely, old_jifs and old_count.)  So we must treat
 151          * jiffies as volatile despite the lock.  We read jiffies
 152          * before latching the timer count to guarantee that although
 153          * the jiffies value might be older than the count (that is,
 154          * the counter may underflow between the last point where
 155          * jiffies was incremented and the point where we latch the
 156          * count), it cannot be newer.
 157          */
 158         jifs = jiffies;
 159         outb_p(0x00, PIT_MODE); /* latch the count ASAP */
 160         count = inb_p(PIT_CH0); /* read the latched count */
 161         count |= inb_p(PIT_CH0) << 8;
 162
 163         /* VIA686a test code... reset the latch if count > max + 1 */
 164         if (count > LATCH) {
 165                 outb_p(0x34, PIT_MODE);
 166                 outb_p(LATCH & 0xff, PIT_CH0);
 167                 outb(LATCH >> 8, PIT_CH0);
 168                 count = LATCH - 1;
 169         }
 170
 171         /*
 172          * It's possible for count to appear to go the wrong way for a
 173          * couple of reasons:
 174          *
 175          *  1. The timer counter underflows, but we haven't handled the
 176          *     resulting interrupt and incremented jiffies yet.
 177          *  2. Hardware problem with the timer, not giving us continuous time,
 178          *     the counter does small "jumps" upwards on some Pentium systems,
 179          *     (see c't 95/10 page 335 for Neptun bug.)
 180          *
 181          * Previous attempts to handle these cases intelligently were
 182          * buggy, so we just do the simple thing now.
 183          */
 184         if (count > old_count && jifs == old_jifs) {
 185                 count = old_count;
 186         }
 187         old_count = count;
 188         old_jifs = jifs;
 189
 190         spin_unlock_irqrestore(&i8253_lock, flags);
 191
 192         count = (LATCH - 1) - count;
 193
 194         return (cycle_t)(jifs * LATCH) + count;
 195 }
 196
 197 static struct clocksource clocksource_pit = {
 198         .name   = "pit",
 199         .rating = 110,
 200         .read   = pit_read,
 201         .mask   = CLOCKSOURCE_MASK(32),
 202         .mult   = 0,
 203         .shift  = 20,
 204 };
 205
 206 static int __init init_pit_clocksource(void)
 207 {
 208         if (num_possible_cpus() > 1) /* PIT does not scale! */
 209                 return 0;
 210
 211         clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
 212         return clocksource_register(&clocksource_pit);
 213 }
 214 arch_initcall(init_pit_clocksource);