1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: STMicroelectronics STM32 ML-AHB interconnect bindings
10 - Fabien Dessenne <fabien.dessenne@st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
16 parts can be accessed through different addresses (see "RAM aliases" in [1])
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
18 among those ports allows to tune the system performance.
19 [1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf
20 [2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping
23 - $ref: /schemas/simple-bus.yaml#
33 Describe memory addresses translation between the local CPU and the
34 remote Cortex-M processor. Each memory region, is declared with
36 - param 1: device base address (Cortex-M processor address)
37 - param 2: physical base address (local CPU address)
38 - param 3: size of the memory region.
56 compatible = "st,mlahb", "simple-bus";
59 reg = <0x10000000 0x40000>;
61 dma-ranges = <0x00000000 0x38000000 0x10000>,
62 <0x10000000 0x10000000 0x60000>,
63 <0x30000000 0x30000000 0x60000>;
65 m4_rproc: m4@10000000 {
66 reg = <0x10000000 0x40000>;