1 High-Frequency PLL (HFPLL)
8 shall contain only one of the following. The generic
9 compatible "qcom,hfpll" should be also included.
11 "qcom,hfpll-ipq8064", "qcom,hfpll"
12 "qcom,hfpll-apq8064", "qcom,hfpll"
13 "qcom,hfpll-msm8974", "qcom,hfpll"
14 "qcom,hfpll-msm8960", "qcom,hfpll"
18 Value type: <prop-encoded-array>
19 Definition: address and size of HPLL registers. An optional second
20 element specifies the address and size of the alias
25 Value type: <prop-encoded-array>
26 Definition: reference to the xo clock.
30 Value type: <stringlist>
31 Definition: must be "xo".
36 Definition: Name of the PLL. Typically hfpllX where X is a CPU number
37 starting at 0. Otherwise hfpll_Y where Y is more specific
42 1) An HFPLL for the L2 cache.
44 clock-controller@f9016000 {
45 compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
46 reg = <0xf9016000 0x30>;
49 clock-output-names = "hfpll_l2";
52 2) An HFPLL for CPU0. This HFPLL has the alias register region.
54 clock-controller@f908a000 {
55 compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
56 reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
59 clock-output-names = "hfpll0";