Documentation/devicetree/bindings/clock/sun8i-de2.txt

   1 Allwinner Display Engine 2.0/3.0 Clock Control Binding
   2 ------------------------------------------------------
   3
   4 Required properties :
   5 - compatible: must contain one of the following compatibles:
   6                 - "allwinner,sun8i-a83t-de2-clk"
   7                 - "allwinner,sun8i-h3-de2-clk"
   8                 - "allwinner,sun8i-v3s-de2-clk"
   9                 - "allwinner,sun50i-a64-de2-clk"
  10                 - "allwinner,sun50i-h5-de2-clk"
  11                 - "allwinner,sun50i-h6-de3-clk"
  12
  13 - reg: Must contain the registers base address and length
  14 - clocks: phandle to the clocks feeding the display engine subsystem.
  15           Three are needed:
  16   - "mod": the display engine module clock (on A83T it's the DE PLL)
  17   - "bus": the bus clock for the whole display engine subsystem
  18 - clock-names: Must contain the clock names described just above
  19 - resets: phandle to the reset control for the display engine subsystem.
  20 - #clock-cells : must contain 1
  21 - #reset-cells : must contain 1
  22
  23 Example:
  24 de2_clocks: clock@1000000 {
  25         compatible = "allwinner,sun8i-h3-de2-clk";
  26         reg = <0x01000000 0x100000>;
  27         clocks = <&ccu CLK_BUS_DE>,
  28                  <&ccu CLK_DE>;
  29         clock-names = "bus",
  30                       "mod";
  31         resets = <&ccu RST_BUS_DE>;
  32         #clock-cells = <1>;
  33         #reset-cells = <1>;
  34 };