| blob | b7f81c63be8bdc33d150a9efa2c41fbbe8d5a4b8 |
1 * Renesas R-Car (RZ/G) DMA Controller Device Tree bindings
3 Renesas R-Car (Gen 2/3) and RZ/G SoCs have multiple multi-channel DMA
4 controller instances named DMAC capable of serving multiple clients. Channels
5 can be dedicated to specific clients or shared between a large number of
6 clients.
8 Each DMA client is connected to one dedicated port of the DMAC, identified by
9 an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
10 256 clients in total. When the number of hardware channels is lower than the
11 number of clients to be served, channels must be shared between multiple DMA
12 clients. The association of DMA clients to DMAC channels is fully dynamic and
13 not described in these device tree bindings.
15 Required Properties:
17 - compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
18 Examples with soctypes are:
19 - "renesas,dmac-r8a7743" (RZ/G1M)
20 - "renesas,dmac-r8a7744" (RZ/G1N)
21 - "renesas,dmac-r8a7745" (RZ/G1E)
22 - "renesas,dmac-r8a77470" (RZ/G1C)
23 - "renesas,dmac-r8a774a1" (RZ/G2M)
24 - "renesas,dmac-r8a774b1" (RZ/G2N)
25 - "renesas,dmac-r8a774c0" (RZ/G2E)
26 - "renesas,dmac-r8a7790" (R-Car H2)
27 - "renesas,dmac-r8a7791" (R-Car M2-W)
28 - "renesas,dmac-r8a7792" (R-Car V2H)
29 - "renesas,dmac-r8a7793" (R-Car M2-N)
30 - "renesas,dmac-r8a7794" (R-Car E2)
31 - "renesas,dmac-r8a7795" (R-Car H3)
32 - "renesas,dmac-r8a7796" (R-Car M3-W)
33 - "renesas,dmac-r8a77961" (R-Car M3-W+)
34 - "renesas,dmac-r8a77965" (R-Car M3-N)
35 - "renesas,dmac-r8a77970" (R-Car V3M)
36 - "renesas,dmac-r8a77980" (R-Car V3H)
37 - "renesas,dmac-r8a77990" (R-Car E3)
38 - "renesas,dmac-r8a77995" (R-Car D3)
40 - reg: base address and length of the registers block for the DMAC
42 - interrupts: interrupt specifiers for the DMAC, one for each entry in
43 interrupt-names.
44 - interrupt-names: one entry for the error interrupt, named "error", plus one
45 entry per channel, named "ch%u", where %u is the channel number ranging from
46 zero to the number of channels minus one.
48 - clock-names: "fck" for the functional clock
49 - clocks: a list of phandle + clock-specifier pairs, one for each entry
50 in clock-names.
51 - clock-names: must contain "fck" for the functional clock.
53 - #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
54 connected to the DMA client
55 - dma-channels: number of DMA channels
57 Example: R8A7790 (R-Car H2) SYS-DMACs
59 dmac0: dma-controller@e6700000 {
60 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
61 reg = <0 0xe6700000 0 0x20000>;
62 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
63 0 200 IRQ_TYPE_LEVEL_HIGH
64 0 201 IRQ_TYPE_LEVEL_HIGH
65 0 202 IRQ_TYPE_LEVEL_HIGH
66 0 203 IRQ_TYPE_LEVEL_HIGH
67 0 204 IRQ_TYPE_LEVEL_HIGH
68 0 205 IRQ_TYPE_LEVEL_HIGH
69 0 206 IRQ_TYPE_LEVEL_HIGH
70 0 207 IRQ_TYPE_LEVEL_HIGH
71 0 208 IRQ_TYPE_LEVEL_HIGH
72 0 209 IRQ_TYPE_LEVEL_HIGH
73 0 210 IRQ_TYPE_LEVEL_HIGH
74 0 211 IRQ_TYPE_LEVEL_HIGH
75 0 212 IRQ_TYPE_LEVEL_HIGH
76 0 213 IRQ_TYPE_LEVEL_HIGH
77 0 214 IRQ_TYPE_LEVEL_HIGH>;
78 interrupt-names = "error",
79 "ch0", "ch1", "ch2", "ch3",
80 "ch4", "ch5", "ch6", "ch7",
81 "ch8", "ch9", "ch10", "ch11",
82 "ch12", "ch13", "ch14";
83 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
84 clock-names = "fck";
85 #dma-cells = <1>;
86 dma-channels = <15>;
87 };
89 dmac1: dma-controller@e6720000 {
90 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
91 reg = <0 0xe6720000 0 0x20000>;
92 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
93 0 216 IRQ_TYPE_LEVEL_HIGH
94 0 217 IRQ_TYPE_LEVEL_HIGH
95 0 218 IRQ_TYPE_LEVEL_HIGH
96 0 219 IRQ_TYPE_LEVEL_HIGH
97 0 308 IRQ_TYPE_LEVEL_HIGH
98 0 309 IRQ_TYPE_LEVEL_HIGH
99 0 310 IRQ_TYPE_LEVEL_HIGH
100 0 311 IRQ_TYPE_LEVEL_HIGH
101 0 312 IRQ_TYPE_LEVEL_HIGH
102 0 313 IRQ_TYPE_LEVEL_HIGH
103 0 314 IRQ_TYPE_LEVEL_HIGH
104 0 315 IRQ_TYPE_LEVEL_HIGH
105 0 316 IRQ_TYPE_LEVEL_HIGH
106 0 317 IRQ_TYPE_LEVEL_HIGH
107 0 318 IRQ_TYPE_LEVEL_HIGH>;
108 interrupt-names = "error",
109 "ch0", "ch1", "ch2", "ch3",
110 "ch4", "ch5", "ch6", "ch7",
111 "ch8", "ch9", "ch10", "ch11",
112 "ch12", "ch13", "ch14";
113 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
114 clock-names = "fck";
115 #dma-cells = <1>;
116 dma-channels = <15>;
117 };