1 Xilinx plb/axi GPIO controller
3 Dual channel GPIO controller with configurable number of pins
4 (from 1 to 32 per channel). Every pin can be configured as
5 input/output/tristate. Both channels share the same global IRQ but
6 local interrupts can be enabled on channel basis.
9 - compatible : Should be "xlnx,xps-gpio-1.00.a"
10 - reg : Address and length of the register set for the device
11 - #gpio-cells : Should be two. The first cell is the pin number and the
12 second cell is used to specify optional parameters (currently unused).
13 - gpio-controller : Marks the device node as a GPIO controller.
16 - interrupts : Interrupt mapping for GPIO IRQ.
17 - xlnx,all-inputs : if n-th bit is setup, GPIO-n is input
18 - xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 1
19 - xlnx,gpio-width : gpio width
20 - xlnx,tri-default : if n-th bit is 1, GPIO-n is in tristate mode
21 - xlnx,is-dual : if 1, controller also uses the second channel
22 - xlnx,all-inputs-2 : as above but for the second channel
23 - xlnx,dout-default-2 : as above but the second channel
24 - xlnx,gpio2-width : as above but for the second channel
25 - xlnx,tri-default-2 : as above but for the second channel
31 compatible = "xlnx,xps-gpio-1.00.a";
33 interrupt-parent = <µblaze_0_intc>;
35 reg = < 0x40000000 0x10000 >;
36 xlnx,all-inputs = <0x0>;
37 xlnx,all-inputs-2 = <0x0>;
38 xlnx,dout-default = <0x0>;
39 xlnx,dout-default-2 = <0x0>;
40 xlnx,gpio-width = <0x2>;
41 xlnx,gpio2-width = <0x2>;
42 xlnx,interrupt-present = <0x1>;
44 xlnx,tri-default = <0xffffffff>;
45 xlnx,tri-default-2 = <0xffffffff>;