Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/gpu/arm,mali-bifrost.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: ARM Mali Bifrost GPU
   8
   9 maintainers:
  10   - Rob Herring <robh@kernel.org>
  11
  12 properties:
  13   $nodename:
  14     pattern: '^gpu@[a-f0-9]+$'
  15
  16   compatible:
  17     items:
  18       - enum:
  19           - amlogic,meson-g12a-mali
  20           - realtek,rtd1619-mali
  21       - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
  22
  23   reg:
  24     maxItems: 1
  25
  26   interrupts:
  27     items:
  28       - description: Job interrupt
  29       - description: MMU interrupt
  30       - description: GPU interrupt
  31
  32   interrupt-names:
  33     items:
  34       - const: job
  35       - const: mmu
  36       - const: gpu
  37
  38   clocks:
  39     maxItems: 1
  40
  41   mali-supply: true
  42
  43   operating-points-v2: true
  44
  45 required:
  46   - compatible
  47   - reg
  48   - interrupts
  49   - interrupt-names
  50   - clocks
  51
  52 allOf:
  53   - if:
  54       properties:
  55         compatible:
  56           contains:
  57             const: amlogic,meson-g12a-mali
  58     then:
  59       properties:
  60         resets:
  61           minItems: 2
  62       required:
  63         - resets
  64
  65 examples:
  66   - |
  67     #include <dt-bindings/interrupt-controller/irq.h>
  68     #include <dt-bindings/interrupt-controller/arm-gic.h>
  69
  70     gpu@ffe40000 {
  71       compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
  72       reg = <0xffe40000 0x10000>;
  73       interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
  74              <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
  75              <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
  76       interrupt-names = "job", "mmu", "gpu";
  77       clocks = <&clk 1>;
  78       mali-supply = <&vdd_gpu>;
  79       operating-points-v2 = <&gpu_opp_table>;
  80       resets = <&reset 0>, <&reset 1>;
  81     };
  82
  83     gpu_opp_table: opp_table0 {
  84       compatible = "operating-points-v2";
  85
  86       opp@533000000 {
  87         opp-hz = /bits/ 64 <533000000>;
  88         opp-microvolt = <1250000>;
  89       };
  90       opp@450000000 {
  91         opp-hz = /bits/ 64 <450000000>;
  92         opp-microvolt = <1150000>;
  93       };
  94       opp@400000000 {
  95         opp-hz = /bits/ 64 <400000000>;
  96         opp-microvolt = <1125000>;
  97       };
  98       opp@350000000 {
  99         opp-hz = /bits/ 64 <350000000>;
 100         opp-microvolt = <1075000>;
 101       };
 102       opp@266000000 {
 103         opp-hz = /bits/ 64 <266000000>;
 104         opp-microvolt = <1025000>;
 105       };
 106       opp@160000000 {
 107         opp-hz = /bits/ 64 <160000000>;
 108         opp-microvolt = <925000>;
 109       };
 110       opp@100000000 {
 111         opp-hz = /bits/ 64 <100000000>;
 112         opp-microvolt = <912500>;
 113       };
 114     };
 115
 116 ...