1 * Synopsys DesignWare I2C
5 - compatible : should be "snps,designware-i2c"
6 or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback
7 - reg : Offset and length of the register set for the device
8 - interrupts : <IRQ> where IRQ is the interrupt number.
9 - clocks : phandles for the clocks, see the description of clock-names below.
10 The phandle for the "ic_clk" clock is required. The phandle for the "pclk"
11 clock is optional. If a single clock is specified but no clock-name, it is
12 the "ic_clk" clock. If both clocks are listed, the "ic_clk" must be first.
14 Recommended properties :
16 - clock-frequency : desired I2C bus clock frequency in Hz.
20 - clock-names : Contains the names of the clocks:
21 "ic_clk", for the core clock used to generate the external I2C clock.
22 "pclk", the interface clock, required for register access.
24 - reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold
25 time, named ICPU_CFG:TWI_DELAY in the datasheet.
27 - i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds.
28 This option is only supported in hardware blocks version 1.11a or newer and
29 on Microsemi SoCs ("mscc,ocelot-i2c" compatible).
31 - i2c-scl-falling-time-ns : should contain the SCL falling time in nanoseconds.
32 This value which is by default 300ns is used to compute the tLOW period.
34 - i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds.
35 This value which is by default 300ns is used to compute the tHIGH period.
42 compatible = "snps,designware-i2c";
43 reg = <0xf0000 0x1000>;
45 clock-frequency = <400000>;
51 compatible = "snps,designware-i2c";
52 reg = <0x1120000 0x1000>;
53 interrupt-parent = <&ictl>;
55 clock-frequency = <400000>;
56 i2c-sda-hold-time-ns = <300>;
57 i2c-sda-falling-time-ns = <300>;
58 i2c-scl-falling-time-ns = <300>;
65 clock-frequency = <400000>;
70 compatible = "linux,slave-24c02";