1 * Amlogic Meson SAR (Successive Approximation Register) A/D converter
4 - compatible: depending on the SoC this should be one of:
5 - "amlogic,meson8-saradc" for Meson8
6 - "amlogic,meson8b-saradc" for Meson8b
7 - "amlogic,meson8m2-saradc" for Meson8m2
8 - "amlogic,meson-gxbb-saradc" for GXBB
9 - "amlogic,meson-gxl-saradc" for GXL
10 - "amlogic,meson-gxm-saradc" for GXM
11 - "amlogic,meson-axg-saradc" for AXG
12 - "amlogic,meson-g12a-saradc" for AXG
13 along with the generic "amlogic,meson-saradc"
14 - reg: the physical base address and length of the registers
15 - interrupts: the interrupt indicating end of sampling
16 - clocks: phandle and clock identifier (see clock-names)
17 - clock-names: mandatory clocks:
18 - "clkin" for the reference clock (typically XTAL)
19 - "core" for the SAR ADC core clock
21 - "adc_clk" for the ADC (sampling) clock
22 - "adc_sel" for the ADC (sampling) clock mux
23 - vref-supply: the regulator supply for the ADC reference voltage
24 - #io-channel-cells: must be 1, see ../iio-bindings.txt
27 - amlogic,hhi-sysctrl: phandle to the syscon which contains the 5th bit
28 of the TSC (temperature sensor coefficient) on
29 Meson8b and Meson8m2 (which used to calibrate the
31 - nvmem-cells: phandle to the temperature_calib eFuse cells
32 - nvmem-cell-names: if present (to enable the temperature sensor
33 calibration) this must contain "temperature_calib"
38 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
39 #io-channel-cells = <1>;
40 reg = <0x0 0x8680 0x0 0x34>;
41 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
43 <&clkc CLKID_SAR_ADC>,
45 <&clkc CLKID_SAR_ADC_CLK>,
46 <&clkc CLKID_SAR_ADC_SEL>;
47 clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";