Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Allwinner A10 Video Engine Device Tree Bindings
   8
   9 maintainers:
  10   - Chen-Yu Tsai <wens@csie.org>
  11   - Maxime Ripard <mripard@kernel.org>
  12
  13 properties:
  14   compatible:
  15     enum:
  16       - allwinner,sun4i-a10-video-engine
  17       - allwinner,sun5i-a13-video-engine
  18       - allwinner,sun7i-a20-video-engine
  19       - allwinner,sun8i-a33-video-engine
  20       - allwinner,sun8i-h3-video-engine
  21       - allwinner,sun50i-a64-video-engine
  22       - allwinner,sun50i-h5-video-engine
  23       - allwinner,sun50i-h6-video-engine
  24
  25   reg:
  26     maxItems: 1
  27
  28   interrupts:
  29     maxItems: 1
  30
  31   clocks:
  32     items:
  33       - description: Bus Clock
  34       - description: Module Clock
  35       - description: RAM Clock
  36
  37   clock-names:
  38     items:
  39       - const: ahb
  40       - const: mod
  41       - const: ram
  42
  43   resets:
  44     maxItems: 1
  45
  46   allwinner,sram:
  47     $ref: /schemas/types.yaml#/definitions/phandle-array
  48     description: Phandle to the device SRAM
  49
  50   memory-region:
  51     description:
  52       CMA pool to use for buffers allocation instead of the default
  53       CMA pool.
  54
  55 required:
  56   - compatible
  57   - reg
  58   - interrupts
  59   - clocks
  60   - clock-names
  61   - resets
  62   - allwinner,sram
  63
  64 additionalProperties: false
  65
  66 examples:
  67   - |
  68     #include <dt-bindings/interrupt-controller/arm-gic.h>
  69     #include <dt-bindings/clock/sun7i-a20-ccu.h>
  70     #include <dt-bindings/reset/sun4i-a10-ccu.h>
  71
  72     video-codec@1c0e000 {
  73         compatible = "allwinner,sun7i-a20-video-engine";
  74         reg = <0x01c0e000 0x1000>;
  75         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
  76         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
  77                  <&ccu CLK_DRAM_VE>;
  78         clock-names = "ahb", "mod", "ram";
  79         resets = <&ccu RST_VE>;
  80         allwinner,sram = <&ve_sram 1>;
  81     };
  82
  83 ...