Documentation/devicetree/bindings/media/cdns,csi2rx.txt

   1 Cadence MIPI-CSI2 RX controller
   2 ===============================
   3
   4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
   5 lanes in input, and 4 different pixel streams in output.
   6
   7 Required properties:
   8   - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
   9   - reg: base address and size of the memory mapped region
  10   - clocks: phandles to the clocks driving the controller
  11   - clock-names: must contain:
  12     * sys_clk: main clock
  13     * p_clk: register bank clock
  14     * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
  15                          implemented in hardware, between 0 and 3
  16
  17 Optional properties:
  18   - phys: phandle to the external D-PHY, phy-names must be provided
  19   - phy-names: must contain "dphy", if the implementation uses an
  20                external D-PHY
  21
  22 Required subnodes:
  23   - ports: A ports node with one port child node per device input and output
  24            port, in accordance with the video interface bindings defined in
  25            Documentation/devicetree/bindings/media/video-interfaces.txt. The
  26            port nodes are numbered as follows:
  27
  28            Port Description
  29            -----------------------------
  30            0    CSI-2 input
  31            1    Stream 0 output
  32            2    Stream 1 output
  33            3    Stream 2 output
  34            4    Stream 3 output
  35
  36            The stream output port nodes are optional if they are not
  37            connected to anything at the hardware level or implemented
  38            in the design.Since there is only one endpoint per port,
  39            the endpoints are not numbered.
  40
  41
  42 Example:
  43
  44 csi2rx: csi-bridge@0d060000 {
  45         compatible = "cdns,csi2rx";
  46         reg = <0x0d060000 0x1000>;
  47         clocks = <&byteclock>, <&byteclock>
  48                  <&coreclock>, <&coreclock>,
  49                  <&coreclock>, <&coreclock>;
  50         clock-names = "sys_clk", "p_clk",
  51                       "pixel_if0_clk", "pixel_if1_clk",
  52                       "pixel_if2_clk", "pixel_if3_clk";
  53
  54         ports {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 port@0 {
  59                         reg = <0>;
  60
  61                         csi2rx_in_sensor: endpoint {
  62                                 remote-endpoint = <&sensor_out_csi2rx>;
  63                                 clock-lanes = <0>;
  64                                 data-lanes = <1 2>;
  65                         };
  66                 };
  67
  68                 port@1 {
  69                         reg = <1>;
  70
  71                         csi2rx_out_grabber0: endpoint {
  72                                 remote-endpoint = <&grabber0_in_csi2rx>;
  73                         };
  74                 };
  75
  76                 port@2 {
  77                         reg = <2>;
  78
  79                         csi2rx_out_grabber1: endpoint {
  80                                 remote-endpoint = <&grabber1_in_csi2rx>;
  81                         };
  82                 };
  83
  84                 port@3 {
  85                         reg = <3>;
  86
  87                         csi2rx_out_grabber2: endpoint {
  88                                 remote-endpoint = <&grabber2_in_csi2rx>;
  89                         };
  90                 };
  91
  92                 port@4 {
  93                         reg = <4>;
  94
  95                         csi2rx_out_grabber3: endpoint {
  96                                 remote-endpoint = <&grabber3_in_csi2rx>;
  97                         };
  98                 };
  99         };
 100 };