Documentation/devicetree/bindings/mfd/bd9571mwv.txt

   1 * ROHM BD9571MWV Power Management Integrated Circuit (PMIC) bindings
   2
   3 Required properties:
   4  - compatible           : Should be "rohm,bd9571mwv".
   5  - reg                  : I2C slave address.
   6  - interrupts           : The interrupt line the device is connected to.
   7  - interrupt-controller : Marks the device node as an interrupt controller.
   8  - #interrupt-cells     : The number of cells to describe an IRQ, should be 2.
   9                             The first cell is the IRQ number.
  10                             The second cell is the flags, encoded as trigger
  11                             masks from ../interrupt-controller/interrupts.txt.
  12  - gpio-controller      : Marks the device node as a GPIO Controller.
  13  - #gpio-cells          : Should be two.  The first cell is the pin number and
  14                             the second cell is used to specify flags.
  15                             See ../gpio/gpio.txt for more information.
  16  - regulators:          : List of child nodes that specify the regulator
  17                             initialization data. Child nodes must be named
  18                             after their hardware counterparts:
  19                              - vd09
  20                              - vd18
  21                              - vd25
  22                              - vd33
  23                              - dvfs
  24                             Each child node is defined using the standard
  25                             binding for regulators.
  26
  27 Optional properties:
  28   - rohm,ddr-backup-power : Value to use for DDR-Backup Power (default 0).
  29                             This is a bitmask that specifies which DDR power
  30                             rails need to be kept powered when backup mode is
  31                             entered, for system suspend:
  32                               - bit 0: DDR0
  33                               - bit 1: DDR1
  34                               - bit 2: DDR0C
  35                               - bit 3: DDR1C
  36                             These bits match the KEEPON_DDR* bits in the
  37                             documentation for the "BKUP Mode Cnt" register.
  38   - rohm,rstbmode-level: The RSTB signal is configured for level mode, to
  39                          accommodate a toggle power switch (the RSTBMODE pin is
  40                          strapped low).
  41   - rohm,rstbmode-pulse: The RSTB signal is configured for pulse mode, to
  42                          accommodate a momentary power switch (the RSTBMODE pin
  43                          is strapped high).
  44                          The two properties above are mutually exclusive.
  45
  46 Example:
  47
  48         pmic: pmic@30 {
  49                 compatible = "rohm,bd9571mwv";
  50                 reg = <0x30>;
  51                 interrupt-parent = <&gpio2>;
  52                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
  53                 interrupt-controller;
  54                 #interrupt-cells = <2>;
  55                 gpio-controller;
  56                 #gpio-cells = <2>;
  57                 rohm,ddr-backup-power = <0xf>;
  58                 rohm,rstbmode-pulse;
  59
  60                 regulators {
  61                         dvfs: dvfs {
  62                                 regulator-name = "dvfs";
  63                                 regulator-min-microvolt = <750000>;
  64                                 regulator-max-microvolt = <1030000>;
  65                                 regulator-boot-on;
  66                                 regulator-always-on;
  67                         };
  68                 };
  69         };