1 # SPDX-License-Identifier: GPL-2.0+
4 $id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR803x PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
15 Bindings for Qualcomm Atheros AR803x PHYs
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
22 description: Clock output frequency in Hertz.
24 - $ref: /schemas/types.yaml#/definitions/uint32
25 - enum: [ 25000000, 50000000, 62500000, 125000000 ]
28 description: Clock output driver strength.
30 - $ref: /schemas/types.yaml#/definitions/uint32
35 If set, keep the PLL enabled even if there is no link. Useful if you
36 want to use the clock output without an ethernet link.
38 Only supported on the AR8031.
43 RGMII I/O voltage regulator (see regulator/regulator.yaml).
45 The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
46 either connect this to the vddio-regulator (1.5V / 1.8V) or the
47 vddh-regulator (2.5V).
49 Only supported on the AR8031.
54 Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V.
56 - $ref: /schemas/regulator/regulator.yaml
61 Dummy subnode to model the external connection of the PHY VDDH
64 - $ref: /schemas/regulator/regulator.yaml
69 #include <dt-bindings/net/qca-ar803x.h>
75 phy-mode = "rgmii-id";
80 qca,clk-out-frequency = <125000000>;
81 qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
83 vddio-supply = <&vddio>;
85 vddio: vddio-regulator {
86 regulator-min-microvolt = <1800000>;
87 regulator-max-microvolt = <1800000>;
92 #include <dt-bindings/net/qca-ar803x.h>
98 phy-mode = "rgmii-id";
103 qca,clk-out-frequency = <50000000>;
104 qca,keep-pll-enabled;
106 vddio-supply = <&vddh>;
108 vddh: vddh-regulator {