Documentation/devicetree/bindings/net/renesas,ether.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/net/renesas,ether.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas Electronics SH EtherMAC
   8
   9 allOf:
  10   - $ref: ethernet-controller.yaml#
  11
  12 maintainers:
  13   - Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
  14
  15 properties:
  16   compatible:
  17     oneOf:
  18       - items:
  19           - enum:
  20               - renesas,gether-r8a7740   # device is a part of R8A7740 SoC
  21               - renesas,gether-r8a77980  # device is a part of R8A77980 SoC
  22               - renesas,ether-r7s72100   # device is a part of R7S72100 SoC
  23               - renesas,ether-r7s9210    # device is a part of R7S9210 SoC
  24       - items:
  25           - enum:
  26               - renesas,ether-r8a7778    # device is a part of R8A7778 SoC
  27               - renesas,ether-r8a7779    # device is a part of R8A7779 SoC
  28           - enum:
  29               - renesas,rcar-gen1-ether  # a generic R-Car Gen1 device
  30       - items:
  31           - enum:
  32               - renesas,ether-r8a7745    # device is a part of R8A7745 SoC
  33               - renesas,ether-r8a7743    # device is a part of R8A7743 SoC
  34               - renesas,ether-r8a7790    # device is a part of R8A7790 SoC
  35               - renesas,ether-r8a7791    # device is a part of R8A7791 SoC
  36               - renesas,ether-r8a7793    # device is a part of R8A7793 SoC
  37               - renesas,ether-r8a7794    # device is a part of R8A7794 SoC
  38           - enum:
  39               - renesas,rcar-gen2-ether  # a generic R-Car Gen2 or RZ/G1 device
  40
  41   reg:
  42     items:
  43        - description: E-DMAC/feLic registers
  44        - description: TSU registers
  45     minItems: 1
  46
  47   interrupts:
  48     maxItems: 1
  49
  50   '#address-cells':
  51     description: number of address cells for the MDIO bus
  52     const: 1
  53
  54   '#size-cells':
  55     description: number of size cells on the MDIO bus
  56     const: 0
  57
  58   clocks:
  59     maxItems: 1
  60
  61   pinctrl-0: true
  62
  63   pinctrl-names: true
  64
  65   renesas,no-ether-link:
  66     type: boolean
  67     description:
  68       specify when a board does not provide a proper Ether LINK signal
  69
  70   renesas,ether-link-active-low:
  71     type: boolean
  72     description:
  73       specify when the Ether LINK signal is active-low instead of normal
  74       active-high
  75
  76 required:
  77   - compatible
  78   - reg
  79   - interrupts
  80   - phy-mode
  81   - phy-handle
  82   - '#address-cells'
  83   - '#size-cells'
  84   - clocks
  85   - pinctrl-0
  86
  87 examples:
  88   # Lager board
  89   - |
  90     #include <dt-bindings/clock/r8a7790-clock.h>
  91     #include <dt-bindings/interrupt-controller/irq.h>
  92
  93     ethernet@ee700000 {
  94         compatible = "renesas,ether-r8a7790", "renesas,rcar-gen2-ether";
  95         reg = <0 0xee700000 0 0x400>;
  96         interrupt-parent = <&gic>;
  97         interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
  98         clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
  99         phy-mode = "rmii";
 100         phy-handle = <&phy1>;
 101         pinctrl-0 = <&ether_pins>;
 102         pinctrl-names = "default";
 103         renesas,ether-link-active-low;
 104         #address-cells = <1>;
 105         #size-cells = <0>;
 106
 107         phy1: ethernet-phy@1 {
 108             reg = <1>;
 109             interrupt-parent = <&irqc0>;
 110             interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 111             pinctrl-0 = <&phy1_pins>;
 112             pinctrl-names = "default";
 113         };
 114     };