1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare MAC Device Tree Bindings
10 - Alexandre Torgue <alexandre.torgue@st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
14 # Select every compatible, including the deprecated ones. This way, we
15 # will be able to report a warning when we have that compatible, since
16 # we will validate the node thanks to the select, but won't report it
17 # as a valid value in the compatible property description
41 # We need to include all the compatibles from schemas that will
42 # include that schemas, otherwise compatible won't validate for
47 - allwinner,sun7i-a20-gmac
48 - allwinner,sun8i-a83t-emac
49 - allwinner,sun8i-h3-emac
50 - allwinner,sun8i-r40-emac
51 - allwinner,sun8i-v3s-emac
52 - allwinner,sun50i-a64-emac
53 - amlogic,meson6-dwmac
54 - amlogic,meson8b-dwmac
55 - amlogic,meson8m2-dwmac
56 - amlogic,meson-gxbb-dwmac
57 - amlogic,meson-axg-dwmac
76 - description: Combined signal for various interrupt events
77 - description: The interrupt to manage the remote wake-up packet detection
78 - description: The interrupt that occurs when Rx exits the LPI state
92 - description: GMAC main clock
93 - description: Peripheral registers interface clock
95 PTP reference clock. This clock is used for programming the
96 Timestamp Addend Register. If not passed then the system
97 clock will be used and this is fine on some platforms.
100 additionalItems: true
116 $ref: ethernet-controller.yaml#/properties/phy-connection-type
118 The property is identical to 'phy-mode', and assumes that there is mode
119 converter in-between the MAC & PHY (e.g. GMII-to-RGMII). This converter
120 can be passive (no SW requirement), and requires that the MAC operate
121 in a different mode than the PHY in order to function.
124 $ref: /schemas/types.yaml#definitions/phandle
126 AXI BUS Mode parameters. Phandle to a node that can contain the
128 * snps,lpi_en, enable Low Power Interface
129 * snps,xit_frm, unlock on WoL
130 * snps,wr_osr_lmt, max write outstanding req. limit
131 * snps,rd_osr_lmt, max read outstanding req. limit
132 * snps,kbbe, do not cross 1KiB boundary.
133 * snps,blen, this is a vector of supported burst length.
134 * snps,fb, fixed-burst
135 * snps,mb, mixed-burst
136 * snps,rb, rebuild INCRx Burst
139 $ref: /schemas/types.yaml#definitions/phandle
141 Multiple RX Queues parameters. Phandle to a node that can
142 contain the following properties
143 * snps,rx-queues-to-use, number of RX queues to be used in the
145 * Choose one of these RX scheduling algorithms
146 * snps,rx-sched-sp, Strict priority
147 * snps,rx-sched-wsp, Weighted Strict priority
149 * Choose one of these modes
150 * snps,dcb-algorithm, Queue to be enabled as DCB
151 * snps,avb-algorithm, Queue to be enabled as AVB
152 * snps,map-to-dma-channel, Channel to map
153 * Specifiy specific packet routing
154 * snps,route-avcp, AV Untagged Control packets
155 * snps,route-ptp, PTP Packets
156 * snps,route-dcbcp, DCB Control Packets
157 * snps,route-up, Untagged Packets
158 * snps,route-multi-broad, Multicast & Broadcast Packets
159 * snps,priority, RX queue priority (Range 0x0 to 0xF)
162 $ref: /schemas/types.yaml#definitions/phandle
164 Multiple TX Queues parameters. Phandle to a node that can
165 contain the following properties
166 * snps,tx-queues-to-use, number of TX queues to be used in the
168 * Choose one of these TX scheduling algorithms
169 * snps,tx-sched-wrr, Weighted Round Robin
170 * snps,tx-sched-wfq, Weighted Fair Queuing
171 * snps,tx-sched-dwrr, Deficit Weighted Round Robin
172 * snps,tx-sched-sp, Strict priority
174 * snps,weight, TX queue weight (if using a DCB weight
176 * Choose one of these modes
177 * snps,dcb-algorithm, TX queue will be working in DCB
178 * snps,avb-algorithm, TX queue will be working in AVB
179 [Attention] Queue 0 is reserved for legacy traffic
180 and so no AVB is available in this queue.
181 * Configure Credit Base Shaper (if AVB Mode selected)
182 * snps,send_slope, enable Low Power Interface
183 * snps,idle_slope, unlock on WoL
184 * snps,high_credit, max write outstanding req. limit
185 * snps,low_credit, max read outstanding req. limit
186 * snps,priority, TX queue priority (Range 0x0 to 0xF)
194 snps,reset-active-low:
196 $ref: /schemas/types.yaml#definitions/flag
198 Indicates that the PHY Reset is active low
200 snps,reset-delays-us:
203 - $ref: /schemas/types.yaml#definitions/uint32-array
207 Triplet of delays. The 1st cell is reset pre-delay in micro
208 seconds. The 2nd cell is reset pulse in micro seconds. The 3rd
209 cell is reset post-delay in micro seconds.
212 $ref: /schemas/types.yaml#definitions/flag
214 Use Address-Aligned Beats
217 $ref: /schemas/types.yaml#definitions/flag
219 Program the DMA to use the fixed burst mode
222 $ref: /schemas/types.yaml#definitions/flag
224 Program the DMA to use the mixed burst mode
226 snps,force_thresh_dma_mode:
227 $ref: /schemas/types.yaml#definitions/flag
229 Force DMA to use the threshold mode for both tx and rx
231 snps,force_sf_dma_mode:
232 $ref: /schemas/types.yaml#definitions/flag
234 Force DMA to use the Store and Forward mode for both tx and
235 rx. This flag is ignored if force_thresh_dma_mode is set.
237 snps,en-tx-lpi-clockgating:
238 $ref: /schemas/types.yaml#definitions/flag
240 Enable gating of the MAC TX clock during TX low-power mode
242 snps,multicast-filter-bins:
243 $ref: /schemas/types.yaml#definitions/uint32
245 Number of multicast filter hash bins supported by this device
248 snps,perfect-filter-entries:
249 $ref: /schemas/types.yaml#definitions/uint32
251 Number of perfect filter entries supported by this device
255 $ref: /schemas/types.yaml#definitions/uint32
257 Port selection speed that can be passed to the core when PCS
258 is supported. For example, this is used in case of SGMII and
264 Creates and registers an MDIO bus.
268 const: snps,dwmac-mdio
281 snps,reset-active-low: ["snps,reset-gpio"]
282 snps,reset-delay-us: ["snps,reset-gpio"]
285 - $ref: "ethernet-controller.yaml#"
291 - allwinner,sun7i-a20-gmac
292 - allwinner,sun8i-a83t-emac
293 - allwinner,sun8i-h3-emac
294 - allwinner,sun8i-r40-emac
295 - allwinner,sun8i-v3s-emac
296 - allwinner,sun50i-a64-emac
305 - $ref: /schemas/types.yaml#definitions/uint32
308 Programmable Burst Length (tx and rx)
312 - $ref: /schemas/types.yaml#definitions/uint32
315 Tx Programmable Burst Length. If set, DMA tx will use this
316 value rather than snps,pbl.
320 - $ref: /schemas/types.yaml#definitions/uint32
323 Rx Programmable Burst Length. If set, DMA rx will use this
324 value rather than snps,pbl.
327 $ref: /schemas/types.yaml#definitions/flag
329 Don\'t multiply the pbl/txpbl/rxpbl values by 8. For core
330 rev < 3.50, don\'t multiply the values by 4.
337 - allwinner,sun7i-a20-gmac
338 - allwinner,sun8i-a83t-emac
339 - allwinner,sun8i-h3-emac
340 - allwinner,sun8i-r40-emac
341 - allwinner,sun8i-v3s-emac
342 - allwinner,sun50i-a64-emac
352 $ref: /schemas/types.yaml#definitions/flag
354 Enables the TSO feature otherwise it will be managed by
355 MAC HW capability register.
359 stmmac_axi_setup: stmmac-axi-config {
360 snps,wr_osr_lmt = <0xf>;
361 snps,rd_osr_lmt = <0xf>;
362 snps,blen = <256 128 64 32 0 0 0>;
365 mtl_rx_setup: rx-queues-config {
366 snps,rx-queues-to-use = <1>;
370 snps,map-to-dma-channel = <0x0>;
371 snps,priority = <0x0>;
375 mtl_tx_setup: tx-queues-config {
376 snps,tx-queues-to-use = <2>;
379 snps,weight = <0x10>;
381 snps,priority = <0x0>;
386 snps,send_slope = <0x1000>;
387 snps,idle_slope = <0x1000>;
388 snps,high_credit = <0x3E800>;
389 snps,low_credit = <0xFFC18000>;
390 snps,priority = <0x1>;
394 gmac0: ethernet@e0800000 {
395 compatible = "snps,dwxgmac-2.10", "snps,dwxgmac";
396 reg = <0xe0800000 0x8000>;
397 interrupt-parent = <&vic1>;
398 interrupts = <24 23 22>;
399 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
400 mac-address = [000000000000]; /* Filled in by U-Boot */
401 max-frame-size = <3800>;
403 snps,multicast-filter-bins = <256>;
404 snps,perfect-filter-entries = <128>;
405 rx-fifo-depth = <16384>;
406 tx-fifo-depth = <16384>;
408 clock-names = "stmmaceth";
409 snps,axi-config = <&stmmac_axi_setup>;
410 snps,mtl-rx-config = <&mtl_rx_setup>;
411 snps,mtl-tx-config = <&mtl_tx_setup>;
413 #address-cells = <1>;
415 compatible = "snps,dwmac-mdio";
416 phy1: ethernet-phy@0 {
422 # FIXME: We should set it, but it would report all the generic
423 # properties as additional properties.
424 # additionalProperties: false