| blob | 4751029b9b7433a7371c007a21c54fe21345a287 |
1 Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings
2 ===================================
4 In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996,
5 the CPU frequencies subset and voltage value of each OPP varies based on
6 the silicon variant in use.
7 Qualcomm Technologies, Inc. Process Voltage Scaling Tables
8 defines the voltage and frequency value based on the msm-id in SMEM
9 and speedbin blown in the efuse combination.
10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
11 to provide the OPP framework with required information (existing HW bitmap).
12 This is used to determine the voltage and frequency value for each OPP of
13 operating-points-v2 table when it is parsed by the OPP framework.
15 Required properties:
16 --------------------
17 In 'cpu' nodes:
18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
20 In 'operating-points-v2' table:
21 - compatible: Should be
22 - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
24 Optional properties:
25 --------------------
26 In 'cpu' nodes:
27 - power-domains: A phandle pointing to the PM domain specifier which provides
28 the performance states available for active state management.
29 Please refer to the power-domains bindings
30 Documentation/devicetree/bindings/power/power_domain.txt
31 and also examples below.
32 - power-domain-names: Should be
33 - 'cpr' for qcs404.
35 In 'operating-points-v2' table:
36 - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
37 efuse registers that has information about the
38 speedbin that is used to select the right frequency/voltage
39 value pair.
40 Please refer the for nvmem-cells
41 bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
42 and also examples below.
44 In every OPP node:
45 - opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
46 Bitmap:
47 0: MSM8996 V3, speedbin 0
48 1: MSM8996 V3, speedbin 1
49 2: MSM8996 V3, speedbin 2
50 3: unused
51 4: MSM8996 SG, speedbin 0
52 5: MSM8996 SG, speedbin 1
53 6: MSM8996 SG, speedbin 2
54 7-31: unused
56 Example 1:
57 ---------
59 cpus {
60 #address-cells = <2>;
61 #size-cells = <0>;
63 CPU0: cpu@0 {
64 device_type = "cpu";
65 compatible = "qcom,kryo";
66 reg = <0x0 0x0>;
67 enable-method = "psci";
68 clocks = <&kryocc 0>;
69 cpu-supply = <&pm8994_s11_saw>;
70 operating-points-v2 = <&cluster0_opp>;
71 #cooling-cells = <2>;
72 next-level-cache = <&L2_0>;
73 L2_0: l2-cache {
74 compatible = "cache";
75 cache-level = <2>;
76 };
77 };
79 CPU1: cpu@1 {
80 device_type = "cpu";
81 compatible = "qcom,kryo";
82 reg = <0x0 0x1>;
83 enable-method = "psci";
84 clocks = <&kryocc 0>;
85 cpu-supply = <&pm8994_s11_saw>;
86 operating-points-v2 = <&cluster0_opp>;
87 #cooling-cells = <2>;
88 next-level-cache = <&L2_0>;
89 };
91 CPU2: cpu@100 {
92 device_type = "cpu";
93 compatible = "qcom,kryo";
94 reg = <0x0 0x100>;
95 enable-method = "psci";
96 clocks = <&kryocc 1>;
97 cpu-supply = <&pm8994_s11_saw>;
98 operating-points-v2 = <&cluster1_opp>;
99 #cooling-cells = <2>;
100 next-level-cache = <&L2_1>;
101 L2_1: l2-cache {
102 compatible = "cache";
103 cache-level = <2>;
104 };
105 };
107 CPU3: cpu@101 {
108 device_type = "cpu";
109 compatible = "qcom,kryo";
110 reg = <0x0 0x101>;
111 enable-method = "psci";
112 clocks = <&kryocc 1>;
113 cpu-supply = <&pm8994_s11_saw>;
114 operating-points-v2 = <&cluster1_opp>;
115 #cooling-cells = <2>;
116 next-level-cache = <&L2_1>;
117 };
119 cpu-map {
120 cluster0 {
121 core0 {
122 cpu = <&CPU0>;
123 };
125 core1 {
126 cpu = <&CPU1>;
127 };
128 };
130 cluster1 {
131 core0 {
132 cpu = <&CPU2>;
133 };
135 core1 {
136 cpu = <&CPU3>;
137 };
138 };
139 };
140 };
142 cluster0_opp: opp_table0 {
143 compatible = "operating-points-v2-kryo-cpu";
144 nvmem-cells = <&speedbin_efuse>;
145 opp-shared;
147 opp-307200000 {
148 opp-hz = /bits/ 64 <307200000>;
149 opp-microvolt = <905000 905000 1140000>;
150 opp-supported-hw = <0x77>;
151 clock-latency-ns = <200000>;
152 };
153 opp-384000000 {
154 opp-hz = /bits/ 64 <384000000>;
155 opp-microvolt = <905000 905000 1140000>;
156 opp-supported-hw = <0x70>;
157 clock-latency-ns = <200000>;
158 };
159 opp-422400000 {
160 opp-hz = /bits/ 64 <422400000>;
161 opp-microvolt = <905000 905000 1140000>;
162 opp-supported-hw = <0x7>;
163 clock-latency-ns = <200000>;
164 };
165 opp-460800000 {
166 opp-hz = /bits/ 64 <460800000>;
167 opp-microvolt = <905000 905000 1140000>;
168 opp-supported-hw = <0x70>;
169 clock-latency-ns = <200000>;
170 };
171 opp-480000000 {
172 opp-hz = /bits/ 64 <480000000>;
173 opp-microvolt = <905000 905000 1140000>;
174 opp-supported-hw = <0x7>;
175 clock-latency-ns = <200000>;
176 };
177 opp-537600000 {
178 opp-hz = /bits/ 64 <537600000>;
179 opp-microvolt = <905000 905000 1140000>;
180 opp-supported-hw = <0x70>;
181 clock-latency-ns = <200000>;
182 };
183 opp-556800000 {
184 opp-hz = /bits/ 64 <556800000>;
185 opp-microvolt = <905000 905000 1140000>;
186 opp-supported-hw = <0x7>;
187 clock-latency-ns = <200000>;
188 };
189 opp-614400000 {
190 opp-hz = /bits/ 64 <614400000>;
191 opp-microvolt = <905000 905000 1140000>;
192 opp-supported-hw = <0x70>;
193 clock-latency-ns = <200000>;
194 };
195 opp-652800000 {
196 opp-hz = /bits/ 64 <652800000>;
197 opp-microvolt = <905000 905000 1140000>;
198 opp-supported-hw = <0x7>;
199 clock-latency-ns = <200000>;
200 };
201 opp-691200000 {
202 opp-hz = /bits/ 64 <691200000>;
203 opp-microvolt = <905000 905000 1140000>;
204 opp-supported-hw = <0x70>;
205 clock-latency-ns = <200000>;
206 };
207 opp-729600000 {
208 opp-hz = /bits/ 64 <729600000>;
209 opp-microvolt = <905000 905000 1140000>;
210 opp-supported-hw = <0x7>;
211 clock-latency-ns = <200000>;
212 };
213 opp-768000000 {
214 opp-hz = /bits/ 64 <768000000>;
215 opp-microvolt = <905000 905000 1140000>;
216 opp-supported-hw = <0x70>;
217 clock-latency-ns = <200000>;
218 };
219 opp-844800000 {
220 opp-hz = /bits/ 64 <844800000>;
221 opp-microvolt = <905000 905000 1140000>;
222 opp-supported-hw = <0x77>;
223 clock-latency-ns = <200000>;
224 };
225 opp-902400000 {
226 opp-hz = /bits/ 64 <902400000>;
227 opp-microvolt = <905000 905000 1140000>;
228 opp-supported-hw = <0x70>;
229 clock-latency-ns = <200000>;
230 };
231 opp-960000000 {
232 opp-hz = /bits/ 64 <960000000>;
233 opp-microvolt = <905000 905000 1140000>;
234 opp-supported-hw = <0x7>;
235 clock-latency-ns = <200000>;
236 };
237 opp-979200000 {
238 opp-hz = /bits/ 64 <979200000>;
239 opp-microvolt = <905000 905000 1140000>;
240 opp-supported-hw = <0x70>;
241 clock-latency-ns = <200000>;
242 };
243 opp-1036800000 {
244 opp-hz = /bits/ 64 <1036800000>;
245 opp-microvolt = <905000 905000 1140000>;
246 opp-supported-hw = <0x7>;
247 clock-latency-ns = <200000>;
248 };
249 opp-1056000000 {
250 opp-hz = /bits/ 64 <1056000000>;
251 opp-microvolt = <905000 905000 1140000>;
252 opp-supported-hw = <0x70>;
253 clock-latency-ns = <200000>;
254 };
255 opp-1113600000 {
256 opp-hz = /bits/ 64 <1113600000>;
257 opp-microvolt = <905000 905000 1140000>;
258 opp-supported-hw = <0x7>;
259 clock-latency-ns = <200000>;
260 };
261 opp-1132800000 {
262 opp-hz = /bits/ 64 <1132800000>;
263 opp-microvolt = <905000 905000 1140000>;
264 opp-supported-hw = <0x70>;
265 clock-latency-ns = <200000>;
266 };
267 opp-1190400000 {
268 opp-hz = /bits/ 64 <1190400000>;
269 opp-microvolt = <905000 905000 1140000>;
270 opp-supported-hw = <0x7>;
271 clock-latency-ns = <200000>;
272 };
273 opp-1209600000 {
274 opp-hz = /bits/ 64 <1209600000>;
275 opp-microvolt = <905000 905000 1140000>;
276 opp-supported-hw = <0x70>;
277 clock-latency-ns = <200000>;
278 };
279 opp-1228800000 {
280 opp-hz = /bits/ 64 <1228800000>;
281 opp-microvolt = <905000 905000 1140000>;
282 opp-supported-hw = <0x7>;
283 clock-latency-ns = <200000>;
284 };
285 opp-1286400000 {
286 opp-hz = /bits/ 64 <1286400000>;
287 opp-microvolt = <1140000 905000 1140000>;
288 opp-supported-hw = <0x70>;
289 clock-latency-ns = <200000>;
290 };
291 opp-1324800000 {
292 opp-hz = /bits/ 64 <1324800000>;
293 opp-microvolt = <1140000 905000 1140000>;
294 opp-supported-hw = <0x5>;
295 clock-latency-ns = <200000>;
296 };
297 opp-1363200000 {
298 opp-hz = /bits/ 64 <1363200000>;
299 opp-microvolt = <1140000 905000 1140000>;
300 opp-supported-hw = <0x72>;
301 clock-latency-ns = <200000>;
302 };
303 opp-1401600000 {
304 opp-hz = /bits/ 64 <1401600000>;
305 opp-microvolt = <1140000 905000 1140000>;
306 opp-supported-hw = <0x5>;
307 clock-latency-ns = <200000>;
308 };
309 opp-1440000000 {
310 opp-hz = /bits/ 64 <1440000000>;
311 opp-microvolt = <1140000 905000 1140000>;
312 opp-supported-hw = <0x70>;
313 clock-latency-ns = <200000>;
314 };
315 opp-1478400000 {
316 opp-hz = /bits/ 64 <1478400000>;
317 opp-microvolt = <1140000 905000 1140000>;
318 opp-supported-hw = <0x1>;
319 clock-latency-ns = <200000>;
320 };
321 opp-1497600000 {
322 opp-hz = /bits/ 64 <1497600000>;
323 opp-microvolt = <1140000 905000 1140000>;
324 opp-supported-hw = <0x4>;
325 clock-latency-ns = <200000>;
326 };
327 opp-1516800000 {
328 opp-hz = /bits/ 64 <1516800000>;
329 opp-microvolt = <1140000 905000 1140000>;
330 opp-supported-hw = <0x70>;
331 clock-latency-ns = <200000>;
332 };
333 opp-1593600000 {
334 opp-hz = /bits/ 64 <1593600000>;
335 opp-microvolt = <1140000 905000 1140000>;
336 opp-supported-hw = <0x71>;
337 clock-latency-ns = <200000>;
338 };
339 opp-1996800000 {
340 opp-hz = /bits/ 64 <1996800000>;
341 opp-microvolt = <1140000 905000 1140000>;
342 opp-supported-hw = <0x20>;
343 clock-latency-ns = <200000>;
344 };
345 opp-2188800000 {
346 opp-hz = /bits/ 64 <2188800000>;
347 opp-microvolt = <1140000 905000 1140000>;
348 opp-supported-hw = <0x10>;
349 clock-latency-ns = <200000>;
350 };
351 };
353 cluster1_opp: opp_table1 {
354 compatible = "operating-points-v2-kryo-cpu";
355 nvmem-cells = <&speedbin_efuse>;
356 opp-shared;
358 opp-307200000 {
359 opp-hz = /bits/ 64 <307200000>;
360 opp-microvolt = <905000 905000 1140000>;
361 opp-supported-hw = <0x77>;
362 clock-latency-ns = <200000>;
363 };
364 opp-384000000 {
365 opp-hz = /bits/ 64 <384000000>;
366 opp-microvolt = <905000 905000 1140000>;
367 opp-supported-hw = <0x70>;
368 clock-latency-ns = <200000>;
369 };
370 opp-403200000 {
371 opp-hz = /bits/ 64 <403200000>;
372 opp-microvolt = <905000 905000 1140000>;
373 opp-supported-hw = <0x7>;
374 clock-latency-ns = <200000>;
375 };
376 opp-460800000 {
377 opp-hz = /bits/ 64 <460800000>;
378 opp-microvolt = <905000 905000 1140000>;
379 opp-supported-hw = <0x70>;
380 clock-latency-ns = <200000>;
381 };
382 opp-480000000 {
383 opp-hz = /bits/ 64 <480000000>;
384 opp-microvolt = <905000 905000 1140000>;
385 opp-supported-hw = <0x7>;
386 clock-latency-ns = <200000>;
387 };
388 opp-537600000 {
389 opp-hz = /bits/ 64 <537600000>;
390 opp-microvolt = <905000 905000 1140000>;
391 opp-supported-hw = <0x70>;
392 clock-latency-ns = <200000>;
393 };
394 opp-556800000 {
395 opp-hz = /bits/ 64 <556800000>;
396 opp-microvolt = <905000 905000 1140000>;
397 opp-supported-hw = <0x7>;
398 clock-latency-ns = <200000>;
399 };
400 opp-614400000 {
401 opp-hz = /bits/ 64 <614400000>;
402 opp-microvolt = <905000 905000 1140000>;
403 opp-supported-hw = <0x70>;
404 clock-latency-ns = <200000>;
405 };
406 opp-652800000 {
407 opp-hz = /bits/ 64 <652800000>;
408 opp-microvolt = <905000 905000 1140000>;
409 opp-supported-hw = <0x7>;
410 clock-latency-ns = <200000>;
411 };
412 opp-691200000 {
413 opp-hz = /bits/ 64 <691200000>;
414 opp-microvolt = <905000 905000 1140000>;
415 opp-supported-hw = <0x70>;
416 clock-latency-ns = <200000>;
417 };
418 opp-729600000 {
419 opp-hz = /bits/ 64 <729600000>;
420 opp-microvolt = <905000 905000 1140000>;
421 opp-supported-hw = <0x7>;
422 clock-latency-ns = <200000>;
423 };
424 opp-748800000 {
425 opp-hz = /bits/ 64 <748800000>;
426 opp-microvolt = <905000 905000 1140000>;
427 opp-supported-hw = <0x70>;
428 clock-latency-ns = <200000>;
429 };
430 opp-806400000 {
431 opp-hz = /bits/ 64 <806400000>;
432 opp-microvolt = <905000 905000 1140000>;
433 opp-supported-hw = <0x7>;
434 clock-latency-ns = <200000>;
435 };
436 opp-825600000 {
437 opp-hz = /bits/ 64 <825600000>;
438 opp-microvolt = <905000 905000 1140000>;
439 opp-supported-hw = <0x70>;
440 clock-latency-ns = <200000>;
441 };
442 opp-883200000 {
443 opp-hz = /bits/ 64 <883200000>;
444 opp-microvolt = <905000 905000 1140000>;
445 opp-supported-hw = <0x7>;
446 clock-latency-ns = <200000>;
447 };
448 opp-902400000 {
449 opp-hz = /bits/ 64 <902400000>;
450 opp-microvolt = <905000 905000 1140000>;
451 opp-supported-hw = <0x70>;
452 clock-latency-ns = <200000>;
453 };
454 opp-940800000 {
455 opp-hz = /bits/ 64 <940800000>;
456 opp-microvolt = <905000 905000 1140000>;
457 opp-supported-hw = <0x7>;
458 clock-latency-ns = <200000>;
459 };
460 opp-979200000 {
461 opp-hz = /bits/ 64 <979200000>;
462 opp-microvolt = <905000 905000 1140000>;
463 opp-supported-hw = <0x70>;
464 clock-latency-ns = <200000>;
465 };
466 opp-1036800000 {
467 opp-hz = /bits/ 64 <1036800000>;
468 opp-microvolt = <905000 905000 1140000>;
469 opp-supported-hw = <0x7>;
470 clock-latency-ns = <200000>;
471 };
472 opp-1056000000 {
473 opp-hz = /bits/ 64 <1056000000>;
474 opp-microvolt = <905000 905000 1140000>;
475 opp-supported-hw = <0x70>;
476 clock-latency-ns = <200000>;
477 };
478 opp-1113600000 {
479 opp-hz = /bits/ 64 <1113600000>;
480 opp-microvolt = <905000 905000 1140000>;
481 opp-supported-hw = <0x7>;
482 clock-latency-ns = <200000>;
483 };
484 opp-1132800000 {
485 opp-hz = /bits/ 64 <1132800000>;
486 opp-microvolt = <905000 905000 1140000>;
487 opp-supported-hw = <0x70>;
488 clock-latency-ns = <200000>;
489 };
490 opp-1190400000 {
491 opp-hz = /bits/ 64 <1190400000>;
492 opp-microvolt = <905000 905000 1140000>;
493 opp-supported-hw = <0x7>;
494 clock-latency-ns = <200000>;
495 };
496 opp-1209600000 {
497 opp-hz = /bits/ 64 <1209600000>;
498 opp-microvolt = <905000 905000 1140000>;
499 opp-supported-hw = <0x70>;
500 clock-latency-ns = <200000>;
501 };
502 opp-1248000000 {
503 opp-hz = /bits/ 64 <1248000000>;
504 opp-microvolt = <905000 905000 1140000>;
505 opp-supported-hw = <0x7>;
506 clock-latency-ns = <200000>;
507 };
508 opp-1286400000 {
509 opp-hz = /bits/ 64 <1286400000>;
510 opp-microvolt = <905000 905000 1140000>;
511 opp-supported-hw = <0x70>;
512 clock-latency-ns = <200000>;
513 };
514 opp-1324800000 {
515 opp-hz = /bits/ 64 <1324800000>;
516 opp-microvolt = <1140000 905000 1140000>;
517 opp-supported-hw = <0x7>;
518 clock-latency-ns = <200000>;
519 };
520 opp-1363200000 {
521 opp-hz = /bits/ 64 <1363200000>;
522 opp-microvolt = <1140000 905000 1140000>;
523 opp-supported-hw = <0x70>;
524 clock-latency-ns = <200000>;
525 };
526 opp-1401600000 {
527 opp-hz = /bits/ 64 <1401600000>;
528 opp-microvolt = <1140000 905000 1140000>;
529 opp-supported-hw = <0x7>;
530 clock-latency-ns = <200000>;
531 };
532 opp-1440000000 {
533 opp-hz = /bits/ 64 <1440000000>;
534 opp-microvolt = <1140000 905000 1140000>;
535 opp-supported-hw = <0x70>;
536 clock-latency-ns = <200000>;
537 };
538 opp-1478400000 {
539 opp-hz = /bits/ 64 <1478400000>;
540 opp-microvolt = <1140000 905000 1140000>;
541 opp-supported-hw = <0x7>;
542 clock-latency-ns = <200000>;
543 };
544 opp-1516800000 {
545 opp-hz = /bits/ 64 <1516800000>;
546 opp-microvolt = <1140000 905000 1140000>;
547 opp-supported-hw = <0x70>;
548 clock-latency-ns = <200000>;
549 };
550 opp-1555200000 {
551 opp-hz = /bits/ 64 <1555200000>;
552 opp-microvolt = <1140000 905000 1140000>;
553 opp-supported-hw = <0x7>;
554 clock-latency-ns = <200000>;
555 };
556 opp-1593600000 {
557 opp-hz = /bits/ 64 <1593600000>;
558 opp-microvolt = <1140000 905000 1140000>;
559 opp-supported-hw = <0x70>;
560 clock-latency-ns = <200000>;
561 };
562 opp-1632000000 {
563 opp-hz = /bits/ 64 <1632000000>;
564 opp-microvolt = <1140000 905000 1140000>;
565 opp-supported-hw = <0x7>;
566 clock-latency-ns = <200000>;
567 };
568 opp-1670400000 {
569 opp-hz = /bits/ 64 <1670400000>;
570 opp-microvolt = <1140000 905000 1140000>;
571 opp-supported-hw = <0x70>;
572 clock-latency-ns = <200000>;
573 };
574 opp-1708800000 {
575 opp-hz = /bits/ 64 <1708800000>;
576 opp-microvolt = <1140000 905000 1140000>;
577 opp-supported-hw = <0x7>;
578 clock-latency-ns = <200000>;
579 };
580 opp-1747200000 {
581 opp-hz = /bits/ 64 <1747200000>;
582 opp-microvolt = <1140000 905000 1140000>;
583 opp-supported-hw = <0x70>;
584 clock-latency-ns = <200000>;
585 };
586 opp-1785600000 {
587 opp-hz = /bits/ 64 <1785600000>;
588 opp-microvolt = <1140000 905000 1140000>;
589 opp-supported-hw = <0x7>;
590 clock-latency-ns = <200000>;
591 };
592 opp-1804800000 {
593 opp-hz = /bits/ 64 <1804800000>;
594 opp-microvolt = <1140000 905000 1140000>;
595 opp-supported-hw = <0x6>;
596 clock-latency-ns = <200000>;
597 };
598 opp-1824000000 {
599 opp-hz = /bits/ 64 <1824000000>;
600 opp-microvolt = <1140000 905000 1140000>;
601 opp-supported-hw = <0x71>;
602 clock-latency-ns = <200000>;
603 };
604 opp-1900800000 {
605 opp-hz = /bits/ 64 <1900800000>;
606 opp-microvolt = <1140000 905000 1140000>;
607 opp-supported-hw = <0x74>;
608 clock-latency-ns = <200000>;
609 };
610 opp-1920000000 {
611 opp-hz = /bits/ 64 <1920000000>;
612 opp-microvolt = <1140000 905000 1140000>;
613 opp-supported-hw = <0x1>;
614 clock-latency-ns = <200000>;
615 };
616 opp-1977600000 {
617 opp-hz = /bits/ 64 <1977600000>;
618 opp-microvolt = <1140000 905000 1140000>;
619 opp-supported-hw = <0x30>;
620 clock-latency-ns = <200000>;
621 };
622 opp-1996800000 {
623 opp-hz = /bits/ 64 <1996800000>;
624 opp-microvolt = <1140000 905000 1140000>;
625 opp-supported-hw = <0x1>;
626 clock-latency-ns = <200000>;
627 };
628 opp-2054400000 {
629 opp-hz = /bits/ 64 <2054400000>;
630 opp-microvolt = <1140000 905000 1140000>;
631 opp-supported-hw = <0x30>;
632 clock-latency-ns = <200000>;
633 };
634 opp-2073600000 {
635 opp-hz = /bits/ 64 <2073600000>;
636 opp-microvolt = <1140000 905000 1140000>;
637 opp-supported-hw = <0x1>;
638 clock-latency-ns = <200000>;
639 };
640 opp-2150400000 {
641 opp-hz = /bits/ 64 <2150400000>;
642 opp-microvolt = <1140000 905000 1140000>;
643 opp-supported-hw = <0x31>;
644 clock-latency-ns = <200000>;
645 };
646 opp-2246400000 {
647 opp-hz = /bits/ 64 <2246400000>;
648 opp-microvolt = <1140000 905000 1140000>;
649 opp-supported-hw = <0x10>;
650 clock-latency-ns = <200000>;
651 };
652 opp-2342400000 {
653 opp-hz = /bits/ 64 <2342400000>;
654 opp-microvolt = <1140000 905000 1140000>;
655 opp-supported-hw = <0x10>;
656 clock-latency-ns = <200000>;
657 };
658 };
660 ....
662 reserved-memory {
663 #address-cells = <2>;
664 #size-cells = <2>;
665 ranges;
666 ....
667 smem_mem: smem-mem@86000000 {
668 reg = <0x0 0x86000000 0x0 0x200000>;
669 no-map;
670 };
671 ....
672 };
674 smem {
675 compatible = "qcom,smem";
676 memory-region = <&smem_mem>;
677 hwlocks = <&tcsr_mutex 3>;
678 };
680 soc {
681 ....
682 qfprom: qfprom@74000 {
683 compatible = "qcom,qfprom";
684 reg = <0x00074000 0x8ff>;
685 #address-cells = <1>;
686 #size-cells = <1>;
687 ....
688 speedbin_efuse: speedbin@133 {
689 reg = <0x133 0x1>;
690 bits = <5 3>;
691 };
692 };
693 };
695 Example 2:
696 ---------
698 cpus {
699 #address-cells = <1>;
700 #size-cells = <0>;
702 CPU0: cpu@100 {
703 device_type = "cpu";
704 compatible = "arm,cortex-a53";
705 reg = <0x100>;
706 ....
707 clocks = <&apcs_glb>;
708 operating-points-v2 = <&cpu_opp_table>;
709 power-domains = <&cpr>;
710 power-domain-names = "cpr";
711 };
713 CPU1: cpu@101 {
714 device_type = "cpu";
715 compatible = "arm,cortex-a53";
716 reg = <0x101>;
717 ....
718 clocks = <&apcs_glb>;
719 operating-points-v2 = <&cpu_opp_table>;
720 power-domains = <&cpr>;
721 power-domain-names = "cpr";
722 };
724 CPU2: cpu@102 {
725 device_type = "cpu";
726 compatible = "arm,cortex-a53";
727 reg = <0x102>;
728 ....
729 clocks = <&apcs_glb>;
730 operating-points-v2 = <&cpu_opp_table>;
731 power-domains = <&cpr>;
732 power-domain-names = "cpr";
733 };
735 CPU3: cpu@103 {
736 device_type = "cpu";
737 compatible = "arm,cortex-a53";
738 reg = <0x103>;
739 ....
740 clocks = <&apcs_glb>;
741 operating-points-v2 = <&cpu_opp_table>;
742 power-domains = <&cpr>;
743 power-domain-names = "cpr";
744 };
745 };
747 cpu_opp_table: cpu-opp-table {
748 compatible = "operating-points-v2-kryo-cpu";
749 opp-shared;
751 opp-1094400000 {
752 opp-hz = /bits/ 64 <1094400000>;
753 required-opps = <&cpr_opp1>;
754 };
755 opp-1248000000 {
756 opp-hz = /bits/ 64 <1248000000>;
757 required-opps = <&cpr_opp2>;
758 };
759 opp-1401600000 {
760 opp-hz = /bits/ 64 <1401600000>;
761 required-opps = <&cpr_opp3>;
762 };
763 };
765 cpr_opp_table: cpr-opp-table {
766 compatible = "operating-points-v2-qcom-level";
768 cpr_opp1: opp1 {
769 opp-level = <1>;
770 qcom,opp-fuse-level = <1>;
771 };
772 cpr_opp2: opp2 {
773 opp-level = <2>;
774 qcom,opp-fuse-level = <2>;
775 };
776 cpr_opp3: opp3 {
777 opp-level = <3>;
778 qcom,opp-fuse-level = <3>;
779 };
780 };
782 ....
784 soc {
785 ....
786 cpr: power-controller@b018000 {
787 compatible = "qcom,qcs404-cpr", "qcom,cpr";
788 reg = <0x0b018000 0x1000>;
789 ....
790 vdd-apc-supply = <&pms405_s3>;
791 #power-domain-cells = <0>;
792 operating-points-v2 = <&cpr_opp_table>;
793 ....
794 };
795 };