| blob | 981b4de128072203f293b5e22dd0d120143f69c8 |
1 * Qualcomm PCI express root complex
3 - compatible:
4 Usage: required
5 Value type: <stringlist>
6 Definition: Value should contain
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-apq8064" for apq8064
9 - "qcom,pcie-apq8084" for apq8084
10 - "qcom,pcie-msm8996" for msm8996 or apq8096
11 - "qcom,pcie-ipq4019" for ipq4019
12 - "qcom,pcie-ipq8074" for ipq8074
13 - "qcom,pcie-qcs404" for qcs404
14 - "qcom,pcie-sdm845" for sdm845
16 - reg:
17 Usage: required
18 Value type: <prop-encoded-array>
19 Definition: Register ranges as listed in the reg-names property
21 - reg-names:
22 Usage: required
23 Value type: <stringlist>
24 Definition: Must include the following entries
25 - "parf" Qualcomm specific registers
26 - "dbi" DesignWare PCIe registers
27 - "elbi" External local bus interface registers
28 - "config" PCIe configuration space
30 - device_type:
31 Usage: required
32 Value type: <string>
33 Definition: Should be "pci". As specified in designware-pcie.txt
35 - #address-cells:
36 Usage: required
37 Value type: <u32>
38 Definition: Should be 3. As specified in designware-pcie.txt
40 - #size-cells:
41 Usage: required
42 Value type: <u32>
43 Definition: Should be 2. As specified in designware-pcie.txt
45 - ranges:
46 Usage: required
47 Value type: <prop-encoded-array>
48 Definition: As specified in designware-pcie.txt
50 - interrupts:
51 Usage: required
52 Value type: <prop-encoded-array>
53 Definition: MSI interrupt
55 - interrupt-names:
56 Usage: required
57 Value type: <stringlist>
58 Definition: Should contain "msi"
60 - #interrupt-cells:
61 Usage: required
62 Value type: <u32>
63 Definition: Should be 1. As specified in designware-pcie.txt
65 - interrupt-map-mask:
66 Usage: required
67 Value type: <prop-encoded-array>
68 Definition: As specified in designware-pcie.txt
70 - interrupt-map:
71 Usage: required
72 Value type: <prop-encoded-array>
73 Definition: As specified in designware-pcie.txt
75 - clocks:
76 Usage: required
77 Value type: <prop-encoded-array>
78 Definition: List of phandle and clock specifier pairs as listed
79 in clock-names property
81 - clock-names:
82 Usage: required
83 Value type: <stringlist>
84 Definition: Should contain the following entries
85 - "iface" Configuration AHB clock
87 - clock-names:
88 Usage: required for ipq/apq8064
89 Value type: <stringlist>
90 Definition: Should contain the following entries
91 - "core" Clocks the pcie hw block
92 - "phy" Clocks the pcie PHY block
93 - clock-names:
94 Usage: required for apq8084/ipq4019
95 Value type: <stringlist>
96 Definition: Should contain the following entries
97 - "aux" Auxiliary (AUX) clock
98 - "bus_master" Master AXI clock
99 - "bus_slave" Slave AXI clock
101 - clock-names:
102 Usage: required for msm8996/apq8096
103 Value type: <stringlist>
104 Definition: Should contain the following entries
105 - "pipe" Pipe Clock driving internal logic
106 - "aux" Auxiliary (AUX) clock
107 - "cfg" Configuration clock
108 - "bus_master" Master AXI clock
109 - "bus_slave" Slave AXI clock
111 - clock-names:
112 Usage: required for ipq8074
113 Value type: <stringlist>
114 Definition: Should contain the following entries
115 - "iface" PCIe to SysNOC BIU clock
116 - "axi_m" AXI Master clock
117 - "axi_s" AXI Slave clock
118 - "ahb" AHB clock
119 - "aux" Auxiliary clock
121 - clock-names:
122 Usage: required for qcs404
123 Value type: <stringlist>
124 Definition: Should contain the following entries
125 - "iface" AHB clock
126 - "aux" Auxiliary clock
127 - "master_bus" AXI Master clock
128 - "slave_bus" AXI Slave clock
130 -clock-names:
131 Usage: required for sdm845
132 Value type: <stringlist>
133 Definition: Should contain the following entries
134 - "aux" Auxiliary clock
135 - "cfg" Configuration clock
136 - "bus_master" Master AXI clock
137 - "bus_slave" Slave AXI clock
138 - "slave_q2a" Slave Q2A clock
139 - "tbu" PCIe TBU clock
140 - "pipe" PIPE clock
142 - resets:
143 Usage: required
144 Value type: <prop-encoded-array>
145 Definition: List of phandle and reset specifier pairs as listed
146 in reset-names property
148 - reset-names:
149 Usage: required for ipq/apq8064
150 Value type: <stringlist>
151 Definition: Should contain the following entries
152 - "axi" AXI reset
153 - "ahb" AHB reset
154 - "por" POR reset
155 - "pci" PCI reset
156 - "phy" PHY reset
158 - reset-names:
159 Usage: required for apq8084
160 Value type: <stringlist>
161 Definition: Should contain the following entries
162 - "core" Core reset
164 - reset-names:
165 Usage: required for ipq/apq8064
166 Value type: <stringlist>
167 Definition: Should contain the following entries
168 - "axi_m" AXI master reset
169 - "axi_s" AXI slave reset
170 - "pipe" PIPE reset
171 - "axi_m_vmid" VMID reset
172 - "axi_s_xpu" XPU reset
173 - "parf" PARF reset
174 - "phy" PHY reset
175 - "axi_m_sticky" AXI sticky reset
176 - "pipe_sticky" PIPE sticky reset
177 - "pwr" PWR reset
178 - "ahb" AHB reset
179 - "phy_ahb" PHY AHB reset
181 - reset-names:
182 Usage: required for ipq8074
183 Value type: <stringlist>
184 Definition: Should contain the following entries
185 - "pipe" PIPE reset
186 - "sleep" Sleep reset
187 - "sticky" Core Sticky reset
188 - "axi_m" AXI Master reset
189 - "axi_s" AXI Slave reset
190 - "ahb" AHB Reset
191 - "axi_m_sticky" AXI Master Sticky reset
193 - reset-names:
194 Usage: required for qcs404
195 Value type: <stringlist>
196 Definition: Should contain the following entries
197 - "axi_m" AXI Master reset
198 - "axi_s" AXI Slave reset
199 - "axi_m_sticky" AXI Master Sticky reset
200 - "pipe_sticky" PIPE sticky reset
201 - "pwr" PWR reset
202 - "ahb" AHB reset
204 - reset-names:
205 Usage: required for sdm845
206 Value type: <stringlist>
207 Definition: Should contain the following entries
208 - "pci" PCIe core reset
210 - power-domains:
211 Usage: required for apq8084 and msm8996/apq8096
212 Value type: <prop-encoded-array>
213 Definition: A phandle and power domain specifier pair to the
214 power domain which is responsible for collapsing
215 and restoring power to the peripheral
217 - vdda-supply:
218 Usage: required
219 Value type: <phandle>
220 Definition: A phandle to the core analog power supply
222 - vdda_phy-supply:
223 Usage: required for ipq/apq8064
224 Value type: <phandle>
225 Definition: A phandle to the analog power supply for PHY
227 - vdda_refclk-supply:
228 Usage: required for ipq/apq8064
229 Value type: <phandle>
230 Definition: A phandle to the analog power supply for IC which generates
231 reference clock
232 - vddpe-3v3-supply:
233 Usage: optional
234 Value type: <phandle>
235 Definition: A phandle to the PCIe endpoint power supply
237 - phys:
238 Usage: required for apq8084 and qcs404
239 Value type: <phandle>
240 Definition: List of phandle(s) as listed in phy-names property
242 - phy-names:
243 Usage: required for apq8084 and qcs404
244 Value type: <stringlist>
245 Definition: Should contain "pciephy"
247 - <name>-gpios:
248 Usage: optional
249 Value type: <prop-encoded-array>
250 Definition: List of phandle and GPIO specifier pairs. Should contain
251 - "perst-gpios" PCIe endpoint reset signal line
252 - "wake-gpios" PCIe endpoint wake signal line
254 * Example for ipq/apq8064
255 pcie@1b500000 {
256 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
257 reg = <0x1b500000 0x1000
258 0x1b502000 0x80
259 0x1b600000 0x100
260 0x0ff00000 0x100000>;
261 reg-names = "dbi", "elbi", "parf", "config";
262 device_type = "pci";
263 linux,pci-domain = <0>;
264 bus-range = <0x00 0xff>;
265 num-lanes = <1>;
266 #address-cells = <3>;
267 #size-cells = <2>;
268 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
269 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
270 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
271 interrupt-names = "msi";
272 #interrupt-cells = <1>;
273 interrupt-map-mask = <0 0 0 0x7>;
274 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
275 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
276 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
277 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
278 clocks = <&gcc PCIE_A_CLK>,
279 <&gcc PCIE_H_CLK>,
280 <&gcc PCIE_PHY_CLK>;
281 clock-names = "core", "iface", "phy";
282 resets = <&gcc PCIE_ACLK_RESET>,
283 <&gcc PCIE_HCLK_RESET>,
284 <&gcc PCIE_POR_RESET>,
285 <&gcc PCIE_PCI_RESET>,
286 <&gcc PCIE_PHY_RESET>;
287 reset-names = "axi", "ahb", "por", "pci", "phy";
288 pinctrl-0 = <&pcie_pins_default>;
289 pinctrl-names = "default";
290 };
292 * Example for apq8084
293 pcie0@fc520000 {
294 compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
295 reg = <0xfc520000 0x2000>,
296 <0xff000000 0x1000>,
297 <0xff001000 0x1000>,
298 <0xff002000 0x2000>;
299 reg-names = "parf", "dbi", "elbi", "config";
300 device_type = "pci";
301 linux,pci-domain = <0>;
302 bus-range = <0x00 0xff>;
303 num-lanes = <1>;
304 #address-cells = <3>;
305 #size-cells = <2>;
306 ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
307 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
308 interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
309 interrupt-names = "msi";
310 #interrupt-cells = <1>;
311 interrupt-map-mask = <0 0 0 0x7>;
312 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
313 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
314 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
315 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
316 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
317 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
318 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
319 <&gcc GCC_PCIE_0_AUX_CLK>;
320 clock-names = "iface", "master_bus", "slave_bus", "aux";
321 resets = <&gcc GCC_PCIE_0_BCR>;
322 reset-names = "core";
323 power-domains = <&gcc PCIE0_GDSC>;
324 vdda-supply = <&pma8084_l3>;
325 phys = <&pciephy0>;
326 phy-names = "pciephy";
327 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
328 pinctrl-0 = <&pcie0_pins_default>;
329 pinctrl-names = "default";
330 };