1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner H3 USB PHY Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
18 const: allwinner,sun8i-h3-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU0 registers
24 - description: PHY PMU1 registers
25 - description: PHY PMU2 registers
26 - description: PHY PMU3 registers
38 - description: USB OTG PHY bus clock
39 - description: USB Host 0 PHY bus clock
40 - description: USB Host 1 PHY bus clock
41 - description: USB Host 2 PHY bus clock
52 - description: USB OTG reset
53 - description: USB Host 1 Controller reset
54 - description: USB Host 2 Controller reset
55 - description: USB Host 3 Controller reset
65 description: GPIO to the USB OTG ID pin
68 description: GPIO to the USB OTG VBUS detect pin
70 usb0_vbus_power-supply:
71 description: Power supply to detect the USB OTG VBUS
74 description: Regulator controlling USB OTG VBUS
77 description: Regulator controlling USB1 Host controller
80 description: Regulator controlling USB2 Host controller
83 description: Regulator controlling USB3 Host controller
95 additionalProperties: false
99 #include <dt-bindings/gpio/gpio.h>
100 #include <dt-bindings/clock/sun8i-h3-ccu.h>
101 #include <dt-bindings/reset/sun8i-h3-ccu.h>
105 compatible = "allwinner,sun8i-h3-usb-phy";
106 reg = <0x01c19400 0x2c>,
111 reg-names = "phy_ctrl",
116 clocks = <&ccu CLK_USB_PHY0>,
120 clock-names = "usb0_phy",
124 resets = <&ccu RST_USB_PHY0>,
128 reset-names = "usb0_reset",
132 usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
133 usb0_vbus-supply = <®_usb0_vbus>;
134 usb1_vbus-supply = <®_usb1_vbus>;
135 usb2_vbus-supply = <®_usb2_vbus>;
136 usb3_vbus-supply = <®_usb3_vbus>;