1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 USB PHY Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
18 const: allwinner,sun9i-a80-usb-phy
25 - description: Main PHY Clock
28 - description: Main PHY clock
29 - description: HSIC 12MHz clock
30 - description: HSIC 480MHz clock
43 - description: Normal USB PHY reset
46 - description: Normal USB PHY reset
47 - description: HSIC Reset
60 When absent, the PHY type will be assumed to be normal USB.
64 Regulator that powers VBUS
75 additionalProperties: false
101 #include <dt-bindings/clock/sun9i-a80-usb.h>
102 #include <dt-bindings/reset/sun9i-a80-usb.h>
104 usbphy1: phy@a00800 {
105 compatible = "allwinner,sun9i-a80-usb-phy";
106 reg = <0x00a00800 0x4>;
107 clocks = <&usb_clocks CLK_USB0_PHY>;
109 resets = <&usb_clocks RST_USB0_PHY>;
111 phy-supply = <®_usb1_vbus>;
116 #include <dt-bindings/clock/sun9i-a80-usb.h>
117 #include <dt-bindings/reset/sun9i-a80-usb.h>
119 usbphy3: phy@a02800 {
120 compatible = "allwinner,sun9i-a80-usb-phy";
121 reg = <0x00a02800 0x4>;
122 clocks = <&usb_clocks CLK_USB2_PHY>,
123 <&usb_clocks CLK_USB_HSIC>,
124 <&usb_clocks CLK_USB2_HSIC>;
128 resets = <&usb_clocks RST_USB2_PHY>,
129 <&usb_clocks RST_USB2_HSIC>;
133 phy-supply = <®_usb3_vbus>;