| blob | 9fb682e47c29b9e6c41cc06c8ea3c14ee92cbc02 |
1 Device tree binding for NVIDIA Tegra XUSB pad controller
2 ========================================================
4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
5 signals) which connect directly to pins/pads on the SoC package. Each lane
6 is controlled by a HW block referred to as a "pad" in the Tegra hardware
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
9 separately configured and powered up.
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
21 device tree node. Each lane exposed by the pad will be represented by its
22 own subnode and can be referenced by users of the lane using the standard
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
25 The Tegra hardware documentation refers to the connection between the XUSB
26 pad controller and the XUSB controller as "ports". This is confusing since
27 "port" is typically used to denote the physical USB receptacle. The device
28 tree binding in this document uses the term "port" to refer to the logical
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
30 for the USB signal, the VBUS power supply, the USB 2.0 companion port for
31 USB 3.0 receptacles, ...).
33 Required properties:
34 --------------------
35 - compatible: Must be:
36 - Tegra124: "nvidia,tegra124-xusb-padctl"
37 - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
38 - Tegra210: "nvidia,tegra210-xusb-padctl"
39 - Tegra186: "nvidia,tegra186-xusb-padctl"
40 - reg: Physical base address and length of the controller's registers.
41 - resets: Must contain an entry for each entry in reset-names.
42 - reset-names: Must include the following entries:
43 - "padctl"
45 For Tegra124:
46 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
47 - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
48 - avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
49 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
51 For Tegra210:
52 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
53 - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
54 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
55 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
57 For Tegra186:
58 - avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
59 power supply. Must supply 1.8 V.
60 - avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
61 3.3 V.
62 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
63 - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
66 Pad nodes:
67 ==========
69 A required child node named "pads" contains a list of subnodes, one for each
70 of the pads exposed by the XUSB pad controller. Each pad may need additional
71 resources that can be referenced in its pad node.
73 The "status" property is used to enable or disable the use of a pad. If set
74 to "disabled", the pad will not be used on the given board. In order to use
75 the pad and any of its lanes, this property must be set to "okay".
77 For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
78 and sata. No extra resources are required for operation of these pads.
80 For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
81 a description of the properties of each pad.
83 UTMI pad:
84 ---------
86 Required properties:
87 - clocks: Must contain an entry for each entry in clock-names.
88 - clock-names: Must contain the following entries:
89 - "trk": phandle and specifier referring to the USB2 tracking clock
91 HSIC pad:
92 ---------
94 Required properties:
95 - clocks: Must contain an entry for each entry in clock-names.
96 - clock-names: Must contain the following entries:
97 - "trk": phandle and specifier referring to the HSIC tracking clock
99 PCIe pad:
100 ---------
102 Required properties:
103 - clocks: Must contain an entry for each entry in clock-names.
104 - clock-names: Must contain the following entries:
105 - "pll": phandle and specifier referring to the PLLE
106 - resets: Must contain an entry for each entry in reset-names.
107 - reset-names: Must contain the following entries:
108 - "phy": reset for the PCIe UPHY block
110 SATA pad:
111 ---------
113 Required properties:
114 - resets: Must contain an entry for each entry in reset-names.
115 - reset-names: Must contain the following entries:
116 - "phy": reset for the SATA UPHY block
119 PHY nodes:
120 ==========
122 Each pad node has a child named "lanes" that contains one or more children of
123 its own, each representing one of the lanes controlled by the pad.
125 Required properties:
126 --------------------
127 - status: Defines the operation status of the PHY. Valid values are:
128 - "disabled": the PHY is disabled
129 - "okay": the PHY is enabled
130 - #phy-cells: Should be 0. Since each lane represents a single PHY, there is
131 no need for an additional specifier.
132 - nvidia,function: The output function of the PHY. See below for a list of
133 valid functions per SoC generation.
135 For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
136 - usb2: usb2-0, usb2-1, usb2-2
137 - functions: "snps", "xusb", "uart"
138 - ulpi: ulpi-0
139 - functions: "snps", "xusb"
140 - hsic: hsic-0, hsic-1
141 - functions: "snps", "xusb"
142 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
143 - functions: "pcie", "usb3-ss"
144 - sata: sata-0
145 - functions: "usb3-ss", "sata"
147 For Tegra210, the list of valid PHY nodes is given below:
148 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
149 - functions: "snps", "xusb", "uart"
150 - hsic: hsic-0, hsic-1
151 - functions: "snps", "xusb"
152 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
153 - functions: "pcie-x1", "usb3-ss", "pcie-x4"
154 - sata: sata-0
155 - functions: "usb3-ss", "sata"
158 Port nodes:
159 ===========
161 A required child node named "ports" contains a list of all the ports exposed
162 by the XUSB pad controller. Per-port configuration is only required for USB.
164 USB2 ports:
165 -----------
167 Required properties:
168 - status: Defines the operation status of the port. Valid values are:
169 - "disabled": the port is disabled
170 - "okay": the port is enabled
171 - mode: A string that determines the mode in which to run the port. Valid
172 values are:
173 - "host": for USB host mode
174 - "device": for USB device mode
175 - "otg": for USB OTG mode
177 Optional properties:
178 - nvidia,internal: A boolean property whose presence determines that a port
179 is internal. In the absence of this property the port is considered to be
180 external.
181 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
183 ULPI ports:
184 -----------
186 Optional properties:
187 - status: Defines the operation status of the port. Valid values are:
188 - "disabled": the port is disabled
189 - "okay": the port is enabled
190 - nvidia,internal: A boolean property whose presence determines that a port
191 is internal. In the absence of this property the port is considered to be
192 external.
193 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
195 HSIC ports:
196 -----------
198 Required properties:
199 - status: Defines the operation status of the port. Valid values are:
200 - "disabled": the port is disabled
201 - "okay": the port is enabled
203 Optional properties:
204 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
206 Super-speed USB ports:
207 ----------------------
209 Required properties:
210 - status: Defines the operation status of the port. Valid values are:
211 - "disabled": the port is disabled
212 - "okay": the port is enabled
213 - nvidia,usb2-companion: A single cell that specifies the physical port number
214 to map this super-speed USB port to. The range of valid port numbers varies
215 with the SoC generation:
216 - 0-2: for Tegra124 and Tegra132
217 - 0-3: for Tegra210
219 Optional properties:
220 - nvidia,internal: A boolean property whose presence determines that a port
221 is internal. In the absence of this property the port is considered to be
222 external.
224 For Tegra124 and Tegra132, the XUSB pad controller exposes the following
225 ports:
226 - 3x USB2: usb2-0, usb2-1, usb2-2
227 - 1x ULPI: ulpi-0
228 - 2x HSIC: hsic-0, hsic-1
229 - 2x super-speed USB: usb3-0, usb3-1
231 For Tegra210, the XUSB pad controller exposes the following ports:
232 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
233 - 2x HSIC: hsic-0, hsic-1
234 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
237 Examples:
238 =========
240 Tegra124 and Tegra132:
241 ----------------------
243 SoC include:
245 padctl@7009f000 {
246 /* for Tegra124 */
247 compatible = "nvidia,tegra124-xusb-padctl";
248 /* for Tegra132 */
249 compatible = "nvidia,tegra132-xusb-padctl",
250 "nvidia,tegra124-xusb-padctl";
251 reg = <0x0 0x7009f000 0x0 0x1000>;
252 resets = <&tegra_car 142>;
253 reset-names = "padctl";
255 pads {
256 usb2 {
257 status = "disabled";
259 lanes {
260 usb2-0 {
261 status = "disabled";
262 #phy-cells = <0>;
263 };
265 usb2-1 {
266 status = "disabled";
267 #phy-cells = <0>;
268 };
270 usb2-2 {
271 status = "disabled";
272 #phy-cells = <0>;
273 };
274 };
275 };
277 ulpi {
278 status = "disabled";
280 lanes {
281 ulpi-0 {
282 status = "disabled";
283 #phy-cells = <0>;
284 };
285 };
286 };
288 hsic {
289 status = "disabled";
291 lanes {
292 hsic-0 {
293 status = "disabled";
294 #phy-cells = <0>;
295 };
297 hsic-1 {
298 status = "disabled";
299 #phy-cells = <0>;
300 };
301 };
302 };
304 pcie {
305 status = "disabled";
307 lanes {
308 pcie-0 {
309 status = "disabled";
310 #phy-cells = <0>;
311 };
313 pcie-1 {
314 status = "disabled";
315 #phy-cells = <0>;
316 };
318 pcie-2 {
319 status = "disabled";
320 #phy-cells = <0>;
321 };
323 pcie-3 {
324 status = "disabled";
325 #phy-cells = <0>;
326 };
328 pcie-4 {
329 status = "disabled";
330 #phy-cells = <0>;
331 };
332 };
333 };
335 sata {
336 status = "disabled";
338 lanes {
339 sata-0 {
340 status = "disabled";
341 #phy-cells = <0>;
342 };
343 };
344 };
345 };
347 ports {
348 usb2-0 {
349 status = "disabled";
350 };
352 usb2-1 {
353 status = "disabled";
354 };
356 usb2-2 {
357 status = "disabled";
358 };
360 ulpi-0 {
361 status = "disabled";
362 };
364 hsic-0 {
365 status = "disabled";
366 };
368 hsic-1 {
369 status = "disabled";
370 };
372 usb3-0 {
373 status = "disabled";
374 };
376 usb3-1 {
377 status = "disabled";
378 };
379 };
380 };
382 Board file:
384 padctl@7009f000 {
385 status = "okay";
387 pads {
388 usb2 {
389 status = "okay";
391 lanes {
392 usb2-0 {
393 nvidia,function = "xusb";
394 status = "okay";
395 };
397 usb2-1 {
398 nvidia,function = "xusb";
399 status = "okay";
400 };
402 usb2-2 {
403 nvidia,function = "xusb";
404 status = "okay";
405 };
406 };
407 };
409 pcie {
410 status = "okay";
412 lanes {
413 pcie-0 {
414 nvidia,function = "usb3-ss";
415 status = "okay";
416 };
418 pcie-2 {
419 nvidia,function = "pcie";
420 status = "okay";
421 };
423 pcie-4 {
424 nvidia,function = "pcie";
425 status = "okay";
426 };
427 };
428 };
430 sata {
431 status = "okay";
433 lanes {
434 sata-0 {
435 nvidia,function = "sata";
436 status = "okay";
437 };
438 };
439 };
440 };
442 ports {
443 /* Micro A/B */
444 usb2-0 {
445 status = "okay";
446 mode = "otg";
447 };
449 /* Mini PCIe */
450 usb2-1 {
451 status = "okay";
452 mode = "host";
453 };
455 /* USB3 */
456 usb2-2 {
457 status = "okay";
458 mode = "host";
460 vbus-supply = <&vdd_usb3_vbus>;
461 };
463 usb3-0 {
464 nvidia,port = <2>;
465 status = "okay";
466 };
467 };
468 };
470 Tegra210:
471 ---------
473 SoC include:
475 padctl@7009f000 {
476 compatible = "nvidia,tegra210-xusb-padctl";
477 reg = <0x0 0x7009f000 0x0 0x1000>;
478 resets = <&tegra_car 142>;
479 reset-names = "padctl";
481 status = "disabled";
483 pads {
484 usb2 {
485 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
486 clock-names = "trk";
487 status = "disabled";
489 lanes {
490 usb2-0 {
491 status = "disabled";
492 #phy-cells = <0>;
493 };
495 usb2-1 {
496 status = "disabled";
497 #phy-cells = <0>;
498 };
500 usb2-2 {
501 status = "disabled";
502 #phy-cells = <0>;
503 };
505 usb2-3 {
506 status = "disabled";
507 #phy-cells = <0>;
508 };
509 };
510 };
512 hsic {
513 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
514 clock-names = "trk";
515 status = "disabled";
517 lanes {
518 hsic-0 {
519 status = "disabled";
520 #phy-cells = <0>;
521 };
523 hsic-1 {
524 status = "disabled";
525 #phy-cells = <0>;
526 };
527 };
528 };
530 pcie {
531 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
532 clock-names = "pll";
533 resets = <&tegra_car 205>;
534 reset-names = "phy";
535 status = "disabled";
537 lanes {
538 pcie-0 {
539 status = "disabled";
540 #phy-cells = <0>;
541 };
543 pcie-1 {
544 status = "disabled";
545 #phy-cells = <0>;
546 };
548 pcie-2 {
549 status = "disabled";
550 #phy-cells = <0>;
551 };
553 pcie-3 {
554 status = "disabled";
555 #phy-cells = <0>;
556 };
558 pcie-4 {
559 status = "disabled";
560 #phy-cells = <0>;
561 };
563 pcie-5 {
564 status = "disabled";
565 #phy-cells = <0>;
566 };
568 pcie-6 {
569 status = "disabled";
570 #phy-cells = <0>;
571 };
572 };
573 };
575 sata {
576 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
577 clock-names = "pll";
578 resets = <&tegra_car 204>;
579 reset-names = "phy";
580 status = "disabled";
582 lanes {
583 sata-0 {
584 status = "disabled";
585 #phy-cells = <0>;
586 };
587 };
588 };
589 };
591 ports {
592 usb2-0 {
593 status = "disabled";
594 };
596 usb2-1 {
597 status = "disabled";
598 };
600 usb2-2 {
601 status = "disabled";
602 };
604 usb2-3 {
605 status = "disabled";
606 };
608 hsic-0 {
609 status = "disabled";
610 };
612 hsic-1 {
613 status = "disabled";
614 };
616 usb3-0 {
617 status = "disabled";
618 };
620 usb3-1 {
621 status = "disabled";
622 };
624 usb3-2 {
625 status = "disabled";
626 };
628 usb3-3 {
629 status = "disabled";
630 };
631 };
632 };
634 Board file:
636 padctl@7009f000 {
637 status = "okay";
639 pads {
640 usb2 {
641 status = "okay";
643 lanes {
644 usb2-0 {
645 nvidia,function = "xusb";
646 status = "okay";
647 };
649 usb2-1 {
650 nvidia,function = "xusb";
651 status = "okay";
652 };
654 usb2-2 {
655 nvidia,function = "xusb";
656 status = "okay";
657 };
659 usb2-3 {
660 nvidia,function = "xusb";
661 status = "okay";
662 };
663 };
664 };
666 pcie {
667 status = "okay";
669 lanes {
670 pcie-0 {
671 nvidia,function = "pcie-x1";
672 status = "okay";
673 };
675 pcie-1 {
676 nvidia,function = "pcie-x4";
677 status = "okay";
678 };
680 pcie-2 {
681 nvidia,function = "pcie-x4";
682 status = "okay";
683 };
685 pcie-3 {
686 nvidia,function = "pcie-x4";
687 status = "okay";
688 };
690 pcie-4 {
691 nvidia,function = "pcie-x4";
692 status = "okay";
693 };
695 pcie-5 {
696 nvidia,function = "usb3-ss";
697 status = "okay";
698 };
700 pcie-6 {
701 nvidia,function = "usb3-ss";
702 status = "okay";
703 };
704 };
705 };
707 sata {
708 status = "okay";
710 lanes {
711 sata-0 {
712 nvidia,function = "sata";
713 status = "okay";
714 };
715 };
716 };
717 };
719 ports {
720 usb2-0 {
721 status = "okay";
722 mode = "otg";
723 };
725 usb2-1 {
726 status = "okay";
727 vbus-supply = <&vdd_5v0_rtl>;
728 mode = "host";
729 };
731 usb2-2 {
732 status = "okay";
733 vbus-supply = <&vdd_usb_vbus>;
734 mode = "host";
735 };
737 usb2-3 {
738 status = "okay";
739 mode = "host";
740 };
742 usb3-0 {
743 status = "okay";
744 nvidia,lanes = "pcie-6";
745 nvidia,port = <1>;
746 };
748 usb3-1 {
749 status = "okay";
750 nvidia,lanes = "pcie-5";
751 nvidia,port = <2>;
752 };
753 };
754 };