Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 # Copyright (C) STMicroelectronics 2019.
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: STM32 GPIO and Pin Mux/Config controller
   9
  10 maintainers:
  11   - Alexandre TORGUE <alexandre.torgue@st.com>
  12
  13 description: |
  14   STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
  15   controller. It controls the input/output settings on the available pins and
  16   also provides ability to multiplex and configure the output of various
  17   on-chip controllers onto these pads.
  18
  19 properties:
  20   compatible:
  21     enum:
  22       - st,stm32f429-pinctrl
  23       - st,stm32f469-pinctrl
  24       - st,stm32f746-pinctrl
  25       - st,stm32f769-pinctrl
  26       - st,stm32h743-pinctrl
  27       - st,stm32mp157-pinctrl
  28       - st,stm32mp157-z-pinctrl
  29
  30   '#address-cells':
  31     const: 1
  32   '#size-cells':
  33     const: 1
  34
  35   ranges: true
  36   pins-are-numbered: true
  37   hwlocks: true
  38
  39   st,syscfg:
  40     allOf:
  41       - $ref: "/schemas/types.yaml#/definitions/phandle-array"
  42     description: Should be phandle/offset/mask
  43       - Phandle to the syscon node which includes IRQ mux selection.
  44       - The offset of the IRQ mux selection register.
  45       - The field mask of IRQ mux, needed if different of 0xf.
  46
  47   st,package:
  48     allOf:
  49       - $ref: /schemas/types.yaml#/definitions/uint32
  50       - enum: [1, 2, 4, 8]
  51     description:
  52      Indicates the SOC package used.
  53      More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
  54
  55
  56 patternProperties:
  57   '^gpio@[0-9a-f]*$':
  58     type: object
  59     properties:
  60       gpio-controller: true
  61       '#gpio-cells':
  62         const: 2
  63
  64       reg:
  65         maxItems: 1
  66       clocks:
  67         maxItems: 1
  68       reset:
  69         minItems: 1
  70         maxItems: 1
  71       gpio-ranges:
  72         minItems: 1
  73         maxItems: 16
  74       ngpios:
  75         description:
  76           Number of available gpios in a bank.
  77         minimum: 1
  78         maximum: 16
  79
  80       st,bank-name:
  81         allOf:
  82           - $ref: "/schemas/types.yaml#/definitions/string"
  83           - enum:
  84             - GPIOA
  85             - GPIOB
  86             - GPIOC
  87             - GPIOD
  88             - GPIOE
  89             - GPIOF
  90             - GPIOG
  91             - GPIOH
  92             - GPIOI
  93             - GPIOJ
  94             - GPIOK
  95             - GPIOZ
  96         description:
  97           Should be a name string for this bank as specified in the datasheet.
  98
  99       st,bank-ioport:
 100         allOf:
 101           - $ref: "/schemas/types.yaml#/definitions/uint32"
 102           - minimum: 0
 103           - maximum: 11
 104
 105         description:
 106           Should correspond to the EXTI IOport selection (EXTI line used
 107           to select GPIOs as interrupts).
 108
 109     required:
 110       - gpio-controller
 111       - '#gpio-cells'
 112       - reg
 113       - clocks
 114       - st,bank-name
 115
 116   '-[0-9]*$':
 117     type: object
 118     patternProperties:
 119       '^pins':
 120         type: object
 121         description: |
 122           A pinctrl node should contain at least one subnode representing the
 123           pinctrl group available on the machine. Each subnode will list the
 124           pins it needs, and how they should be configured, with regard to muxer
 125           configuration, pullups, drive, output high/low and output speed.
 126         properties:
 127           pinmux:
 128             allOf:
 129               - $ref: "/schemas/types.yaml#/definitions/uint32-array"
 130             description: |
 131               Integer array, represents gpio pin number and mux setting.
 132               Supported pin number and mux varies for different SoCs, and are
 133               defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
 134               These defines are calculated as: ((port * 16 + line) << 8) | function
 135               With:
 136               - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
 137               - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
 138               - function: The function number, can be:
 139               * 0 : GPIO
 140               * 1 : Alternate Function 0
 141               * 2 : Alternate Function 1
 142               * 3 : Alternate Function 2
 143               * ...
 144               * 16 : Alternate Function 15
 145               * 17 : Analog
 146               To simplify the usage, macro is available to generate "pinmux" field.
 147               This macro is available here:
 148                 - include/dt-bindings/pinctrl/stm32-pinfunc.h
 149               Some examples of using macro:
 150                /* GPIO A9 set as alernate function 2 */
 151                ... {
 152                           pinmux = <STM32_PINMUX('A', 9, AF2)>;
 153                };
 154                /* GPIO A9 set as GPIO  */
 155                ... {
 156                           pinmux = <STM32_PINMUX('A', 9, GPIO)>;
 157                };
 158                /* GPIO A9 set as analog */
 159                ... {
 160                           pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
 161                };
 162
 163           bias-disable:
 164             type: boolean
 165           bias-pull-down:
 166             type: boolean
 167           bias-pull-up:
 168             type: boolean
 169           drive-push-pull:
 170             type: boolean
 171           drive-open-drain:
 172             type: boolean
 173           output-low:
 174             type: boolean
 175           output-high:
 176             type: boolean
 177           slew-rate:
 178             description: |
 179               0: Low speed
 180               1: Medium speed
 181               2: Fast speed
 182               3: High speed
 183             allOf:
 184               - $ref: /schemas/types.yaml#/definitions/uint32
 185               - enum: [0, 1, 2, 3]
 186
 187         required:
 188           - pinmux
 189
 190 required:
 191   - compatible
 192   - '#address-cells'
 193   - '#size-cells'
 194   - ranges
 195   - pins-are-numbered
 196
 197 examples:
 198   - |
 199     #include <dt-bindings/pinctrl/stm32-pinfunc.h>
 200     #include <dt-bindings/mfd/stm32f4-rcc.h>
 201     //Example 1
 202       pinctrl@40020000 {
 203               #address-cells = <1>;
 204               #size-cells = <1>;
 205               compatible = "st,stm32f429-pinctrl";
 206               ranges = <0 0x40020000 0x3000>;
 207               pins-are-numbered;
 208
 209               gpioa: gpio@0 {
 210                       gpio-controller;
 211                       #gpio-cells = <2>;
 212                       reg = <0x0 0x400>;
 213                       resets = <&reset_ahb1 0>;
 214                       clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
 215                       st,bank-name = "GPIOA";
 216               };
 217        };
 218
 219     //Example 2 (using gpio-ranges)
 220       pinctrl@50020000 {
 221               #address-cells = <1>;
 222               #size-cells = <1>;
 223               compatible = "st,stm32f429-pinctrl";
 224               ranges = <0 0x50020000 0x3000>;
 225               pins-are-numbered;
 226
 227               gpiob: gpio@1000 {
 228                       gpio-controller;
 229                       #gpio-cells = <2>;
 230                       reg = <0x1000 0x400>;
 231                       resets = <&reset_ahb1 0>;
 232                       clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
 233                       st,bank-name = "GPIOB";
 234                       gpio-ranges = <&pinctrl 0 0 16>;
 235               };
 236
 237               gpioc: gpio@2000 {
 238                       gpio-controller;
 239                       #gpio-cells = <2>;
 240                       reg = <0x2000 0x400>;
 241                       resets = <&reset_ahb1 0>;
 242                       clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
 243                       st,bank-name = "GPIOC";
 244                       ngpios = <5>;
 245                       gpio-ranges = <&pinctrl 0 16 3>,
 246                                     <&pinctrl 14 30 2>;
 247               };
 248       };
 249
 250     //Example 3 pin groups
 251       pinctrl@60020000 {
 252         usart1_pins_a: usart1-0 {
 253                 pins1 {
 254                         pinmux = <STM32_PINMUX('A', 9, AF7)>;
 255                         bias-disable;
 256                         drive-push-pull;
 257                         slew-rate = <0>;
 258                 };
 259                 pins2 {
 260                         pinmux = <STM32_PINMUX('A', 10, AF7)>;
 261                         bias-disable;
 262                 };
 263         };
 264     };
 265
 266     usart1 {
 267                 pinctrl-0 = <&usart1_pins_a>;
 268                 pinctrl-names = "default";
 269     };
 270
 271 ...