1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC PWM timers
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
17 outputs - see SoC and board manual).
19 Be aware that the clocksource driver supports only uniprocessor systems.
27 - samsung,s3c2410-pwm # 16-bit, S3C24xx
28 - samsung,s3c6400-pwm # 32-bit, S3C64xx
29 - samsung,s5p6440-pwm # 32-bit, S5P64x0
30 - samsung,s5pc100-pwm # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs
31 - samsung,exynos4210-pwm # 32-bit, Exynos
42 Should contain all following required clock names:
43 - "timers" - PWM base clock used to generate PWM signals,
44 and any subset of following optional clock names:
45 - "pwm-tclk0" - first external PWM clock source,
46 - "pwm-tclk1" - second external PWM clock source.
47 Note that not all IP variants allow using all external clock sources.
48 Refer to SoC documentation to learn which clock source configurations
66 One interrupt per timer, starting at timer 0.
72 The only third cell flag supported by this binding
73 is PWM_POLARITY_INVERTED.
78 A list of PWM channels used as PWM outputs on particular platform.
79 It is an array of up to 5 elements being indices of PWM channels
80 (from 0 to 4), the order does not matter.
82 - $ref: /schemas/types.yaml#/definitions/uint32-array
96 additionalProperties: false
101 compatible = "samsung,s3c6400-pwm";
102 reg = <0x7f006000 0x1000>;
103 interrupt-parent = <&vic0>;
104 interrupts = <23>, <24>, <25>, <27>, <28>;
105 clocks = <&clock 67>;
106 clock-names = "timers";
107 samsung,pwm-outputs = <0>, <1>;