1 DT bindings for the Renesas R-Car and RZ/G Reset Controllers
3 The R-Car and RZ/G Reset Controllers provide reset control, and implement the
5 - Latching of the levels on mode pins when PRESET# is negated,
6 - Mode monitoring register,
7 - Reset control of peripheral devices (on R-Car Gen1),
8 - Watchdog timer (on R-Car Gen1),
9 - Register-based reset control and boot address registers for the various CPU
10 cores (on R-Car Gen2 and Gen3, and on RZ/G).
14 - compatible: Should be
15 - "renesas,<soctype>-reset-wdt" for R-Car Gen1,
16 - "renesas,<soctype>-rst" for R-Car Gen2 and Gen3, and RZ/G
17 Examples with soctypes are:
18 - "renesas,r8a7743-rst" (RZ/G1M)
19 - "renesas,r8a7744-rst" (RZ/G1N)
20 - "renesas,r8a7745-rst" (RZ/G1E)
21 - "renesas,r8a77470-rst" (RZ/G1C)
22 - "renesas,r8a774a1-rst" (RZ/G2M)
23 - "renesas,r8a774b1-rst" (RZ/G2N)
24 - "renesas,r8a774c0-rst" (RZ/G2E)
25 - "renesas,r8a7778-reset-wdt" (R-Car M1A)
26 - "renesas,r8a7779-reset-wdt" (R-Car H1)
27 - "renesas,r8a7790-rst" (R-Car H2)
28 - "renesas,r8a7791-rst" (R-Car M2-W)
29 - "renesas,r8a7792-rst" (R-Car V2H
30 - "renesas,r8a7793-rst" (R-Car M2-N)
31 - "renesas,r8a7794-rst" (R-Car E2)
32 - "renesas,r8a7795-rst" (R-Car H3)
33 - "renesas,r8a7796-rst" (R-Car M3-W)
34 - "renesas,r8a77961-rst" (R-Car M3-W+)
35 - "renesas,r8a77965-rst" (R-Car M3-N)
36 - "renesas,r8a77970-rst" (R-Car V3M)
37 - "renesas,r8a77980-rst" (R-Car V3H)
38 - "renesas,r8a77990-rst" (R-Car E3)
39 - "renesas,r8a77995-rst" (R-Car D3)
40 - reg: Address start and address range for the device.
45 rst: reset-controller@e6160000 {
46 compatible = "renesas,r8a7795-rst";
47 reg = <0 0xe6160000 0 0x0200>;