1 * Freescale low power universal asynchronous receiver/transmitter (lpuart)
5 - "fsl,vf610-lpuart" for lpuart compatible with the one integrated
6 on Vybrid vf610 SoC with 8-bit register organization
7 - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated
8 on LS1021A SoC with 32-bit big-endian register organization
9 - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated
10 on i.MX7ULP SoC with 32-bit little-endian register organization
11 - "fsl,imx8qxp-lpuart" for lpuart compatible with the one integrated
12 on i.MX8QXP SoC with 32-bit little-endian register organization
13 - "fsl,imx8qm-lpuart" for lpuart compatible with the one integrated
14 on i.MX8QM SoC with 32-bit little-endian register organization
15 - reg : Address and length of the register set for the device
16 - interrupts : Should contain uart interrupt
17 - clocks : phandle + clock specifier pairs, one for each entry in clock-names
18 - clock-names : For vf610/ls1021a/imx7ulp, "ipg" clock is for uart bus/baud
19 clock. For imx8qxp lpuart, "ipg" clock is bus clock that is used to access
20 lpuart controller registers, it also requires "baud" clock for module to
21 receive/transmit data.
24 - dmas: A list of two dma specifiers, one for each entry in dma-names.
25 - dma-names: should contain "tx" and "rx".
26 - rs485-rts-active-low, linux,rs485-enabled-at-boot-time: see rs485.txt
28 Note: Optional properties for DMA support. Write them both or both not.
32 uart0: serial@40027000 {
33 compatible = "fsl,vf610-lpuart";
34 reg = <0x40027000 0x1000>;
35 interrupts = <0 61 0x00>;
36 clocks = <&clks VF610_CLK_UART0>;
40 dma-names = "rx","tx";