Documentation/devicetree/bindings/serial/sifive-serial.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: SiFive asynchronous serial interface (UART)
   8
   9 maintainers:
  10   - Pragnesh Patel <pragnesh.patel@sifive.com>
  11   - Paul Walmsley  <paul.walmsley@sifive.com>
  12   - Palmer Dabbelt <palmer@sifive.com>
  13
  14 allOf:
  15   - $ref: /schemas/serial.yaml#
  16
  17 properties:
  18   compatible:
  19     items:
  20       - const: sifive,fu540-c000-uart
  21       - const: sifive,uart0
  22
  23     description:
  24       Should be something similar to "sifive,<chip>-uart"
  25       for the UART as integrated on a particular chip,
  26       and "sifive,uart<version>" for the general UART IP
  27       block programming model.
  28
  29       UART HDL that corresponds to the IP block version
  30       numbers can be found here -
  31
  32       https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
  33
  34   reg:
  35     maxItems: 1
  36
  37   interrupts:
  38     maxItems: 1
  39
  40   clocks:
  41     maxItems: 1
  42
  43 required:
  44   - compatible
  45   - reg
  46   - interrupts
  47   - clocks
  48
  49 additionalProperties: false
  50
  51 examples:
  52   - |
  53       #include <dt-bindings/clock/sifive-fu540-prci.h>
  54       serial@10010000 {
  55         compatible = "sifive,fu540-c000-uart", "sifive,uart0";
  56         interrupt-parent = <&plic0>;
  57         interrupts = <80>;
  58         reg = <0x0 0x10010000 0x0 0x1000>;
  59         clocks = <&prci PRCI_CLK_TLCLK>;
  60       };
  61
  62 ...