Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt

   1 Qualcomm Quad Serial Peripheral Interface (QSPI)
   2
   3 The QSPI controller allows SPI protocol communication in single, dual, or quad
   4 wire transmission modes for read/write access to slaves such as NOR flash.
   5
   6 Required properties:
   7 - compatible:   An SoC specific identifier followed by "qcom,qspi-v1", such as
   8                 "qcom,sdm845-qspi", "qcom,qspi-v1"
   9 - reg:          Should contain the base register location and length.
  10 - interrupts:   Interrupt number used by the controller.
  11 - clocks:       Should contain the core and AHB clock.
  12 - clock-names:  Should be "core" for core clock and "iface" for AHB clock.
  13
  14 SPI slave nodes must be children of the SPI master node and can contain
  15 properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
  16
  17 Example:
  18
  19         qspi: spi@88df000 {
  20                 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
  21                 reg = <0x88df000 0x600>;
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  25                 clock-names = "iface", "core";
  26                 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
  27                          <&gcc GCC_QSPI_CORE_CLK>;
  28
  29                 flash@0 {
  30                         compatible = "jedec,spi-nor";
  31                         reg = <0>;
  32                         spi-max-frequency = <25000000>;
  33                         spi-tx-bus-width = <2>;
  34                         spi-rx-bus-width = <2>;
  35                 };
  36         };