1 Tegra124 SOCTHERM thermal management system
3 The SOCTHERM IP block contains thermal sensors, support for polled
4 or interrupt-based thermal monitoring, CPU and GPU throttling based
5 on temperature trip points, and handling external overcurrent
6 notifications. It is also used to manage emergency shutdown in an
10 - compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
11 For Tegra132, must contain "nvidia,tegra132-soctherm".
12 For Tegra210, must contain "nvidia,tegra210-soctherm".
13 - reg : Should contain at least 2 entries for each entry in reg-names:
14 - SOCTHERM register set
15 - Tegra CAR register set: Required for Tegra124 and Tegra210.
16 - CCROC register set: Required for Tegra132.
17 - reg-names : Should contain at least 2 entries:
21 - interrupts : Defines the interrupt used by SOCTHERM
22 - clocks : Must contain an entry for each entry in clock-names.
23 See ../clocks/clock-bindings.txt for details.
24 - clock-names : Must include the following entries:
27 - resets : Must contain an entry for each entry in reset-names.
28 See ../reset/reset.txt for details.
29 - reset-names : Must include the following entries:
31 - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description
32 of this property. See <dt-bindings/thermal/tegra124-soctherm.h> for a
33 list of valid values when referring to thermal sensors.
34 - throttle-cfgs: A sub-node which is a container of configuration for each
35 hardware throttle events. These events can be set as cooling devices.
36 * throttle events: Sub-nodes must be named as "light" or "heavy".
38 - nvidia,priority: Each throttles has its own throttle settings, so the
39 SW need to set priorities for various throttle, the HW arbiter can select
40 the final throttle settings.
41 Bigger value indicates higher priority, In general, higher priority
42 translates to lower target frequency. SW needs to ensure that critical
43 thermal alarms are given higher priority, and ensure that there is
44 no race if priority of two vectors is set to the same value.
45 The range of this value is 1~100.
46 - nvidia,cpu-throt-percent: This property is for Tegra124 and Tegra210.
47 It is the throttling depth of pulse skippers, it's the percentage
49 - nvidia,cpu-throt-level: This property is only for Tegra132, it is the
50 level of pulse skippers, which used to throttle clock frequencies. It
51 indicates cpu clock throttling depth, and the depth can be programmed.
52 Must set as following values:
53 TEGRA_SOCTHERM_THROT_LEVEL_LOW, TEGRA_SOCTHERM_THROT_LEVEL_MED
54 TEGRA_SOCTHERM_THROT_LEVEL_HIGH, TEGRA_SOCTHERM_THROT_LEVEL_NONE
55 - nvidia,gpu-throt-level: This property is for Tegra124 and Tegra210.
56 It is the level of pulse skippers, which used to throttle clock
57 frequencies. It indicates gpu clock throttling depth and can be
58 programmed to any of the following values which represent a throttling
60 TEGRA_SOCTHERM_THROT_LEVEL_NONE (0%)
61 TEGRA_SOCTHERM_THROT_LEVEL_LOW (50%),
62 TEGRA_SOCTHERM_THROT_LEVEL_MED (75%),
63 TEGRA_SOCTHERM_THROT_LEVEL_HIGH (85%).
64 - #cooling-cells: Should be 1. This cooling device only support on/off state.
65 See ./thermal.txt for a description of this property.
67 Optional properties: The following properties are T210 specific and
68 valid only for OCx throttle events.
69 - nvidia,count-threshold: Specifies the number of OC events that are
70 required for triggering an interrupt. Interrupts are not triggered if
71 the property is missing. A value of 0 will interrupt on every OC alarm.
72 - nvidia,polarity-active-low: Configures the polarity of the OC alaram
73 signal. If present, this means assert low, otherwise assert high.
74 - nvidia,alarm-filter: Number of clocks to filter event. When the filter
75 expires (which means the OC event has not occurred for a long time),
76 the counter is cleared and filter is rearmed. Default value is 0.
77 - nvidia,throttle-period-us: Specifies the number of uSec for which
78 throttling is engaged after the OC event is deasserted. Default value
82 - nvidia,thermtrips : When present, this property specifies the temperature at
83 which the soctherm hardware will assert the thermal trigger signal to the
84 Power Management IC, which can be configured to reset or shutdown the device.
85 It is an array of pairs where each pair represents a tsensor id followed by a
86 temperature in milli Celcius. In the absence of this property the critical
87 trip point will be used for thermtrip temperature.
90 - the "critical" type trip points will be used to set the temperature at which
91 the SOC_THERM hardware will assert a thermal trigger if the "nvidia,thermtrips"
92 property is missing. When the thermtrips property is present, the breach of a
93 critical trip point is reported back to the thermal framework to implement
96 - the "hot" type trip points will be set to SOC_THERM hardware as the throttle
97 temperature. Once the the temperature of this thermal zone is higher
98 than it, it will trigger the HW throttle event.
103 compatible = "nvidia,tegra124-soctherm";
104 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
105 0x0 0x60006000 0x0 0x400 /* CAR reg_base */
106 reg-names = "soctherm-reg", "car-reg";
107 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
109 <&tegra_car TEGRA124_CLK_SOC_THERM>;
110 clock-names = "tsensor", "soctherm";
111 resets = <&tegra_car 78>;
112 reset-names = "soctherm";
114 #thermal-sensor-cells = <1>;
116 nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500
117 TEGRA124_SOCTHERM_SENSOR_GPU 103000>;
121 * When the "heavy" cooling device triggered,
122 * the HW will skip cpu clock's pulse in 85% depth,
123 * skip gpu clock's pulse in 85% level
125 throttle_heavy: heavy {
126 nvidia,priority = <100>;
127 nvidia,cpu-throt-percent = <85>;
128 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
130 #cooling-cells = <1>;
134 * When the "light" cooling device triggered,
135 * the HW will skip cpu clock's pulse in 50% depth,
136 * skip gpu clock's pulse in 50% level
138 throttle_light: light {
139 nvidia,priority = <80>;
140 nvidia,cpu-throt-percent = <50>;
141 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>;
143 #cooling-cells = <1>;
147 * If these two devices are triggered in same time, the HW throttle
148 * arbiter will select the highest priority as the final throttle
149 * settings to skip cpu pulse.
153 nvidia,priority = <50>;
154 nvidia,polarity-active-low;
155 nvidia,count-threshold = <100>;
156 nvidia,alarm-filter = <5100000>;
157 nvidia,throttle-period-us = <0>;
158 nvidia,cpu-throt-percent = <75>;
159 nvidia,gpu-throt-level =
160 <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
165 Example: referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" :
168 compatible = "nvidia,tegra132-soctherm";
169 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
170 0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */;
171 reg-names = "soctherm-reg", "ccroc-reg";
175 * When the "heavy" cooling device triggered,
176 * the HW will skip cpu clock's pulse in HIGH level
178 throttle_heavy: heavy {
179 nvidia,priority = <100>;
180 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
182 #cooling-cells = <1>;
186 * When the "light" cooling device triggered,
187 * the HW will skip cpu clock's pulse in MED level
189 throttle_light: light {
190 nvidia,priority = <80>;
191 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
193 #cooling-cells = <1>;
197 * If these two devices are triggered in same time, the HW throttle
198 * arbiter will select the highest priority as the final throttle
199 * settings to skip cpu pulse.
205 Example: referring to thermal sensors :
209 polling-delay-passive = <1000>;
210 polling-delay = <1000>;
213 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
216 cpu_shutdown_trip: shutdown-trip {
217 temperature = <102500>;
222 cpu_throttle_trip: throttle-trip {
223 temperature = <100000>;
231 trip = <&cpu_throttle_trip>;
232 cooling-device = <&throttle_heavy 1 1>;