Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: TI J721e UFS Host Controller Glue Driver
   8
   9 maintainers:
  10   - Vignesh Raghavendra <vigneshr@ti.com>
  11
  12 properties:
  13   compatible:
  14     items:
  15       - const: ti,j721e-ufs
  16
  17   reg:
  18     maxItems: 1
  19     description: address of TI UFS glue registers
  20
  21   clocks:
  22     maxItems: 1
  23     description: phandle to the M-PHY clock
  24
  25   power-domains:
  26     maxItems: 1
  27
  28 required:
  29   - compatible
  30   - reg
  31   - clocks
  32   - power-domains
  33
  34 patternProperties:
  35   "^ufs@[0-9a-f]+$":
  36     type: object
  37     description: |
  38       Cadence UFS controller node must be the child node. Refer
  39       Documentation/devicetree/bindings/ufs/cdns,ufshc.txt for binding
  40       documentation of child node
  41
  42 examples:
  43   - |
  44     #include <dt-bindings/interrupt-controller/irq.h>
  45     #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47     ufs_wrapper: ufs-wrapper@4e80000 {
  48        compatible = "ti,j721e-ufs";
  49        reg = <0x0 0x4e80000 0x0 0x100>;
  50        power-domains = <&k3_pds 277>;
  51        clocks = <&k3_clks 277 1>;
  52        assigned-clocks = <&k3_clks 277 1>;
  53        assigned-clock-parents = <&k3_clks 277 4>;
  54        #address-cells = <2>;
  55        #size-cells = <2>;
  56
  57        ufs@4e84000 {
  58           compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
  59           reg = <0x0 0x4e84000 0x0 0x10000>;
  60           interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  61           freq-table-hz = <19200000 19200000>;
  62           power-domains = <&k3_pds 277>;
  63           clocks = <&k3_clks 277 1>;
  64           assigned-clocks = <&k3_clks 277 1>;
  65           assigned-clock-parents = <&k3_clks 277 4>;
  66           clock-names = "core_clk";
  67        };
  68     };