1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
9 select ARCH_HAS_DMA_PREP_COHERENT
10 select ARCH_HAS_PTE_SPECIAL
11 select ARCH_HAS_SETUP_DMA_OPS
12 select ARCH_HAS_SYNC_DMA_FOR_CPU
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
14 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
15 select ARCH_32BIT_OFF_T
16 select BUILDTIME_TABLE_SORT
17 select CLONE_BACKWARDS
19 select DMA_DIRECT_REMAP
20 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
21 select GENERIC_CLOCKEVENTS
22 select GENERIC_FIND_FIRST_BIT
23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
24 select GENERIC_IRQ_SHOW
25 select GENERIC_PCI_IOMAP
26 select GENERIC_PENDING_IRQ if SMP
27 select GENERIC_SCHED_CLOCK
28 select GENERIC_SMP_IDLE_THREAD
30 select HAVE_ARCH_TRACEHOOK
31 select HAVE_COPY_THREAD_TLS
32 select HAVE_DEBUG_STACKOVERFLOW
33 select HAVE_DEBUG_KMEMLEAK
34 select HAVE_FUTEX_CMPXCHG if FUTEX
35 select HAVE_IOREMAP_PROT
36 select HAVE_KERNEL_GZIP
37 select HAVE_KERNEL_LZMA
39 select HAVE_KRETPROBES
40 select HAVE_MOD_ARCH_SPECIFIC
42 select HAVE_PERF_EVENTS
43 select HANDLE_DOMAIN_IRQ
45 select MODULES_USE_ELF_RELA
47 select OF_EARLY_FLATTREE
48 select PCI_SYSCALL if PCI
49 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
50 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
52 config ARCH_HAS_CACHE_LINE_SIZE
55 config TRACE_IRQFLAGS_SUPPORT
58 config LOCKDEP_SUPPORT
61 config SCHED_OMIT_FRAME_POINTER
67 config ARCH_DISCONTIGMEM_ENABLE
70 config ARCH_FLATMEM_ENABLE
79 config GENERIC_CALIBRATE_DELAY
82 config GENERIC_HWEIGHT
85 config STACKTRACE_SUPPORT
89 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
93 menu "ARC Architecture Configuration"
95 menu "ARC Platform/SoC/Board"
97 source "arch/arc/plat-tb10x/Kconfig"
98 source "arch/arc/plat-axs10x/Kconfig"
99 #New platform adds here
100 source "arch/arc/plat-eznps/Kconfig"
101 source "arch/arc/plat-hsdk/Kconfig"
106 prompt "ARC Instruction Set"
111 select CPU_NO_EFFICIENT_FFS
113 The original ARC ISA of ARC600/700 cores
117 select ARC_TIMERS_64BIT
119 ISA for the Next Generation ARC-HS cores
123 menu "ARC CPU Configuration"
127 default ARC_CPU_770 if ISA_ARCOMPACT
128 default ARC_CPU_HS if ISA_ARCV2
136 Support for ARC750 core
142 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
143 This core has a bunch of cool new features:
144 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
145 Shared Address Spaces (for sharing TLB entries in MMU)
146 -Caches: New Prog Model, Region Flush
147 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
155 Support for ARC HS38x Cores based on ARCv2 ISA
156 The notable features are:
157 - SMP configurations of upto 4 core with coherency
158 - Optional L2 Cache and IO-Coherency
159 - Revised Interrupt Architecture (multiple priorites, reg banks,
160 auto stack switch, auto regfile save/restore)
161 - MMUv4 (PIPT dcache, Huge Pages)
163 * 64bit load/store: LDD, STD
164 * Hardware assisted divide/remainder: DIV, REM
165 * Function prologue/epilogue: ENTER_S, LEAVE_S
166 * IRQ enable/disable: CLRI, SETI
167 * pop count: FFS, FLS
168 * SETcc, BMSKN, XBFU...
172 config CPU_BIG_ENDIAN
173 bool "Enable Big Endian Mode"
175 Build kernel for Big Endian Mode of ARC CPU
178 bool "Symmetric Multi-Processing"
179 select ARC_MCIP if ISA_ARCV2
181 This enables support for systems with more than one CPU.
186 int "Maximum number of CPUs (2-4096)"
190 config ARC_SMP_HALT_ON_RESET
191 bool "Enable Halt-on-reset boot mode"
193 In SMP configuration cores can be configured as Halt-on-reset
194 or they could all start at same time. For Halt-on-reset, non
195 masters are parked until Master kicks them so they can start of
196 at designated entry point. For other case, all jump to common
197 entry point and spin wait for Master's signal.
202 bool "ARConnect Multicore IP (MCIP) Support "
206 This IP block enables SMP in ARC-HS38 cores.
207 It provides for cross-core interrupts, multi-core debug
208 hardware semaphores, shared memory,....
211 bool "Enable Cache Support"
216 config ARC_CACHE_LINE_SHIFT
217 int "Cache Line Length (as power of 2)"
221 Starting with ARC700 4.9, Cache line length is configurable,
222 This option specifies "N", with Line-len = 2 power N
223 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
224 Linux only supports same line lengths for I and D caches.
226 config ARC_HAS_ICACHE
227 bool "Use Instruction Cache"
230 config ARC_HAS_DCACHE
231 bool "Use Data Cache"
234 config ARC_CACHE_PAGES
235 bool "Per Page Cache Control"
237 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
239 This can be used to over-ride the global I/D Cache Enable on a
240 per-page basis (but only for pages accessed via MMU such as
241 Kernel Virtual address or User Virtual Address)
242 TLB entries have a per-page Cache Enable Bit.
243 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
244 Global DISABLE + Per Page ENABLE won't work
246 config ARC_CACHE_VIPT_ALIASING
247 bool "Support VIPT Aliasing D$"
248 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
255 Single Cycle RAMS to store Fast Path Code
258 int "ICCM Size in KB"
260 depends on ARC_HAS_ICCM
265 Single Cycle RAMS to store Fast Path Data
268 int "DCCM Size in KB"
270 depends on ARC_HAS_DCCM
273 hex "DCCM map address"
275 depends on ARC_HAS_DCCM
279 default ARC_MMU_V3 if ARC_CPU_770
280 default ARC_MMU_V2 if ARC_CPU_750D
281 default ARC_MMU_V4 if ARC_CPU_HS
293 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
294 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
298 depends on ARC_CPU_770
300 Introduced with ARC700 4.10: New Features
301 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
302 Shared Address Spaces (SASID)
314 prompt "MMU Page Size"
315 default ARC_PAGE_SIZE_8K
317 config ARC_PAGE_SIZE_8K
320 Choose between 8k vs 16k
322 config ARC_PAGE_SIZE_16K
324 depends on ARC_MMU_V3 || ARC_MMU_V4
326 config ARC_PAGE_SIZE_4K
328 depends on ARC_MMU_V3 || ARC_MMU_V4
333 prompt "MMU Super Page Size"
334 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
335 default ARC_HUGEPAGE_2M
337 config ARC_HUGEPAGE_2M
340 config ARC_HUGEPAGE_16M
346 int "Maximum NUMA Nodes (as a power of 2)"
347 default "0" if !DISCONTIGMEM
348 default "1" if DISCONTIGMEM
349 depends on NEED_MULTIPLE_NODES
351 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
354 config ARC_COMPACT_IRQ_LEVELS
355 depends on ISA_ARCOMPACT
356 bool "Setup Timer IRQ as high Priority"
357 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
360 config ARC_FPU_SAVE_RESTORE
361 bool "Enable FPU state persistence across context switch"
363 ARCompact FPU has internal registers to assist with Double precision
364 Floating Point operations. There are control and stauts registers
365 for floating point exceptions and rounding modes. These are
366 preserved across task context switch when enabled.
372 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
374 depends on !ARC_CANT_LLSC
377 bool "Insn: SWAPE (endian-swap)"
382 config ARC_USE_UNALIGNED_MEM_ACCESS
383 bool "Enable unaligned access in HW"
385 select HAVE_EFFICIENT_UNALIGNED_ACCESS
387 The ARC HS architecture supports unaligned memory access
388 which is disabled by default. Enable unaligned access in
389 hardware and use software to use it
392 bool "Insn: 64bit LDD/STD"
394 Enable gcc to generate 64-bit load/store instructions
395 ISA mandates even/odd registers to allow encoding of two
396 dest operands with 2 possible source operands.
399 config ARC_HAS_DIV_REM
400 bool "Insn: div, divu, rem, remu"
403 config ARC_HAS_ACCL_REGS
404 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
407 Depending on the configuration, CPU can contain accumulator reg-pair
408 (also referred to as r58:r59). These can also be used by gcc as GPR so
409 kernel needs to save/restore per process
411 config ARC_IRQ_NO_AUTOSAVE
412 bool "Disable hardware autosave regfile on interrupts"
415 On HS cores, taken interrupt auto saves the regfile on stack.
416 This is programmable and can be optionally disabled in which case
417 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
421 endmenu # "ARC CPU Configuration"
423 config LINUX_LINK_BASE
424 hex "Kernel link address"
427 ARC700 divides the 32 bit phy address space into two equal halves
428 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
429 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
430 Typically Linux kernel is linked at the start of untransalted addr,
431 hence the default value of 0x8zs.
432 However some customers have peripherals mapped at this addr, so
433 Linux needs to be scooted a bit.
434 If you don't know what the above means, leave this setting alone.
435 This needs to match memory start address specified in Device Tree
437 config LINUX_RAM_BASE
438 hex "RAM base address"
439 default LINUX_LINK_BASE
441 By default Linux is linked at base of RAM. However in some special
442 cases (such as HSDK), Linux can't be linked at start of DDR, hence
446 bool "High Memory Support"
447 select ARCH_DISCONTIGMEM_ENABLE
449 With ARC 2G:2G address split, only upper 2G is directly addressable by
450 kernel. Enable this to potentially allow access to rest of 2G and PAE
454 bool "Support for the 40-bit Physical Address Extension"
457 select PHYS_ADDR_T_64BIT
459 Enable access to physical memory beyond 4G, only supported on
460 ARC cores with 40 bit Physical Addressing support
462 config ARC_KVADDR_SIZE
463 int "Kernel Virtual Address Space size (MB)"
467 The kernel address space is carved out of 256MB of translated address
468 space for catering to vmalloc, modules, pkmap, fixmap. This however may
469 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
470 this to be stretched to 512 MB (by extending into the reserved
473 config ARC_CURR_IN_REG
474 bool "Dedicate Register r25 for current_task pointer"
477 This reserved Register R25 to point to Current Task in
478 kernel mode. This saves memory access for each such access
481 config ARC_EMUL_UNALIGNED
482 bool "Emulate unaligned memory access (userspace only)"
483 select SYSCTL_ARCH_UNALIGN_NO_WARN
484 select SYSCTL_ARCH_UNALIGN_ALLOW
485 depends on ISA_ARCOMPACT
487 This enables misaligned 16 & 32 bit memory access from user space.
488 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
489 potential bugs in code
492 int "Timer Frequency"
495 config ARC_METAWARE_HLINK
496 bool "Support for Metaware debugger assisted Host access"
498 This options allows a Linux userland apps to directly access
499 host file system (open/creat/read/write etc) with help from
500 Metaware Debugger. This can come in handy for Linux-host communication
501 when there is no real usable peripheral such as EMAC.
509 config ARC_DW2_UNWIND
510 bool "Enable DWARF specific kernel stack unwind"
514 Compiles the kernel with DWARF unwind information and can be used
515 to get stack backtraces.
517 If you say Y here the resulting kernel image will be slightly larger
518 but not slower, and it will give very useful debugging information.
519 If you don't debug the kernel, you can say N, but we may not be able
520 to solve problems without frame unwind information
522 config ARC_DBG_TLB_PARANOIA
523 bool "Paranoia Checks in Low Level TLB Handlers"
525 config ARC_DBG_JUMP_LABEL
526 bool "Paranoid checks in Static Keys (jump labels) code"
527 depends on JUMP_LABEL
528 default y if STATIC_KEYS_SELFTEST
530 Enable paranoid checks and self-test of both ARC-specific and generic
531 part of static keys (jump labels) related code.
534 config ARC_BUILTIN_DTB_NAME
535 string "Built in DTB"
537 Set the name of the DTB to embed in the vmlinux binary
538 Leaving it blank selects the minimal "skeleton" dtb
540 endmenu # "ARC Architecture Configuration"
542 config FORCE_MAX_ZONEORDER
543 int "Maximum zone order"
544 default "12" if ARC_HUGEPAGE_16M
547 source "kernel/power/Kconfig"