arch/arc/include/asm/mmu_context.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   4  *
   5  * vineetg: May 2011
   6  *  -Refactored get_new_mmu_context( ) to only handle live-mm.
   7  *   retiring-mm handled in other hooks
   8  *
   9  * Vineetg: March 25th, 2008: Bug #92690
  10  *  -Major rewrite of Core ASID allocation routine get_new_mmu_context
  11  *
  12  * Amit Bhor, Sameer Dhavale: Codito Technologies 2004
  13  */
  14
  15 #ifndef _ASM_ARC_MMU_CONTEXT_H
  16 #define _ASM_ARC_MMU_CONTEXT_H
  17
  18 #include <asm/arcregs.h>
  19 #include <asm/tlb.h>
  20 #include <linux/sched/mm.h>
  21
  22 #include <asm-generic/mm_hooks.h>
  23
  24 /*              ARC700 ASID Management
  25  *
  26  * ARC MMU provides 8-bit ASID (0..255) to TAG TLB entries, allowing entries
  27  * with same vaddr (different tasks) to co-exit. This provides for
  28  * "Fast Context Switch" i.e. no TLB flush on ctxt-switch
  29  *
  30  * Linux assigns each task a unique ASID. A simple round-robin allocation
  31  * of H/w ASID is done using software tracker @asid_cpu.
  32  * When it reaches max 255, the allocation cycle starts afresh by flushing
  33  * the entire TLB and wrapping ASID back to zero.
  34  *
  35  * A new allocation cycle, post rollover, could potentially reassign an ASID
  36  * to a different task. Thus the rule is to refresh the ASID in a new cycle.
  37  * The 32 bit @asid_cpu (and mm->asid) have 8 bits MMU PID and rest 24 bits
  38  * serve as cycle/generation indicator and natural 32 bit unsigned math
  39  * automagically increments the generation when lower 8 bits rollover.
  40  */
  41
  42 #define MM_CTXT_ASID_MASK       0x000000ff /* MMU PID reg :8 bit PID */
  43 #define MM_CTXT_CYCLE_MASK      (~MM_CTXT_ASID_MASK)
  44
  45 #define MM_CTXT_FIRST_CYCLE     (MM_CTXT_ASID_MASK + 1)
  46 #define MM_CTXT_NO_ASID         0UL
  47
  48 #define asid_mm(mm, cpu)        mm->context.asid[cpu]
  49 #define hw_pid(mm, cpu)         (asid_mm(mm, cpu) & MM_CTXT_ASID_MASK)
  50
  51 DECLARE_PER_CPU(unsigned int, asid_cache);
  52 #define asid_cpu(cpu)           per_cpu(asid_cache, cpu)
  53
  54 /*
  55  * Get a new ASID if task doesn't have a valid one (unalloc or from prev cycle)
  56  * Also set the MMU PID register to existing/updated ASID
  57  */
  58 static inline void get_new_mmu_context(struct mm_struct *mm)
  59 {
  60         const unsigned int cpu = smp_processor_id();
  61         unsigned long flags;
  62
  63         local_irq_save(flags);
  64
  65         /*
  66          * Move to new ASID if it was not from current alloc-cycle/generation.
  67          * This is done by ensuring that the generation bits in both mm->ASID
  68          * and cpu's ASID counter are exactly same.
  69          *
  70          * Note: Callers needing new ASID unconditionally, independent of
  71          *       generation, e.g. local_flush_tlb_mm() for forking  parent,
  72          *       first need to destroy the context, setting it to invalid
  73          *       value.
  74          */
  75         if (!((asid_mm(mm, cpu) ^ asid_cpu(cpu)) & MM_CTXT_CYCLE_MASK))
  76                 goto set_hw;
  77
  78         /* move to new ASID and handle rollover */
  79         if (unlikely(!(++asid_cpu(cpu) & MM_CTXT_ASID_MASK))) {
  80
  81                 local_flush_tlb_all();
  82
  83                 /*
  84                  * Above check for rollover of 8 bit ASID in 32 bit container.
  85                  * If the container itself wrapped around, set it to a non zero
  86                  * "generation" to distinguish from no context
  87                  */
  88                 if (!asid_cpu(cpu))
  89                         asid_cpu(cpu) = MM_CTXT_FIRST_CYCLE;
  90         }
  91
  92         /* Assign new ASID to tsk */
  93         asid_mm(mm, cpu) = asid_cpu(cpu);
  94
  95 set_hw:
  96         write_aux_reg(ARC_REG_PID, hw_pid(mm, cpu) | MMU_ENABLE);
  97
  98         local_irq_restore(flags);
  99 }
 100
 101 /*
 102  * Initialize the context related info for a new mm_struct
 103  * instance.
 104  */
 105 static inline int
 106 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 107 {
 108         int i;
 109
 110         for_each_possible_cpu(i)
 111                 asid_mm(mm, i) = MM_CTXT_NO_ASID;
 112
 113         return 0;
 114 }
 115
 116 static inline void destroy_context(struct mm_struct *mm)
 117 {
 118         unsigned long flags;
 119
 120         /* Needed to elide CONFIG_DEBUG_PREEMPT warning */
 121         local_irq_save(flags);
 122         asid_mm(mm, smp_processor_id()) = MM_CTXT_NO_ASID;
 123         local_irq_restore(flags);
 124 }
 125
 126 /* Prepare the MMU for task: setup PID reg with allocated ASID
 127     If task doesn't have an ASID (never alloc or stolen, get a new ASID)
 128 */
 129 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 130                              struct task_struct *tsk)
 131 {
 132         const int cpu = smp_processor_id();
 133
 134         /*
 135          * Note that the mm_cpumask is "aggregating" only, we don't clear it
 136          * for the switched-out task, unlike some other arches.
 137          * It is used to enlist cpus for sending TLB flush IPIs and not sending
 138          * it to CPUs where a task once ran-on, could cause stale TLB entry
 139          * re-use, specially for a multi-threaded task.
 140          * e.g. T1 runs on C1, migrates to C3. T2 running on C2 munmaps.
 141          *      For a non-aggregating mm_cpumask, IPI not sent C1, and if T1
 142          *      were to re-migrate to C1, it could access the unmapped region
 143          *      via any existing stale TLB entries.
 144          */
 145         cpumask_set_cpu(cpu, mm_cpumask(next));
 146
 147 #ifdef ARC_USE_SCRATCH_REG
 148         /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
 149         write_aux_reg(ARC_REG_SCRATCH_DATA0, next->pgd);
 150 #endif
 151
 152         get_new_mmu_context(next);
 153 }
 154
 155 /*
 156  * Called at the time of execve() to get a new ASID
 157  * Note the subtlety here: get_new_mmu_context() behaves differently here
 158  * vs. in switch_mm(). Here it always returns a new ASID, because mm has
 159  * an unallocated "initial" value, while in latter, it moves to a new ASID,
 160  * only if it was unallocated
 161  */
 162 #define activate_mm(prev, next)         switch_mm(prev, next, NULL)
 163
 164 /* it seemed that deactivate_mm( ) is a reasonable place to do book-keeping
 165  * for retiring-mm. However destroy_context( ) still needs to do that because
 166  * between mm_release( ) = >deactive_mm( ) and
 167  * mmput => .. => __mmdrop( ) => destroy_context( )
 168  * there is a good chance that task gets sched-out/in, making it's ASID valid
 169  * again (this teased me for a whole day).
 170  */
 171 #define deactivate_mm(tsk, mm)   do { } while (0)
 172
 173 #define enter_lazy_tlb(mm, tsk)
 174
 175 #endif /* __ASM_ARC_MMU_CONTEXT_H */