arch/arc/kernel/setup.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   4  */
   5
   6 #include <linux/seq_file.h>
   7 #include <linux/fs.h>
   8 #include <linux/delay.h>
   9 #include <linux/root_dev.h>
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/clocksource.h>
  13 #include <linux/console.h>
  14 #include <linux/module.h>
  15 #include <linux/cpu.h>
  16 #include <linux/of_fdt.h>
  17 #include <linux/of.h>
  18 #include <linux/cache.h>
  19 #include <uapi/linux/mount.h>
  20 #include <asm/sections.h>
  21 #include <asm/arcregs.h>
  22 #include <asm/tlb.h>
  23 #include <asm/setup.h>
  24 #include <asm/page.h>
  25 #include <asm/irq.h>
  26 #include <asm/unwind.h>
  27 #include <asm/mach_desc.h>
  28 #include <asm/smp.h>
  29
  30 #define FIX_PTR(x)  __asm__ __volatile__(";" : "+r"(x))
  31
  32 unsigned int intr_to_DE_cnt;
  33
  34 /* Part of U-boot ABI: see head.S */
  35 int __initdata uboot_tag;
  36 int __initdata uboot_magic;
  37 char __initdata *uboot_arg;
  38
  39 const struct machine_desc *machine_desc;
  40
  41 struct task_struct *_current_task[NR_CPUS];     /* For stack switching */
  42
  43 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
  44
  45 static const struct id_to_str arc_legacy_rel[] = {
  46         /* ID.ARCVER,   Release */
  47 #ifdef CONFIG_ISA_ARCOMPACT
  48         { 0x34,         "R4.10"},
  49         { 0x35,         "R4.11"},
  50 #else
  51         { 0x51,         "R2.0" },
  52         { 0x52,         "R2.1" },
  53         { 0x53,         "R3.0" },
  54 #endif
  55         { 0x00,         NULL   }
  56 };
  57
  58 static const struct id_to_str arc_cpu_rel[] = {
  59         /* UARCH.MAJOR, Release */
  60         {  0,           "R3.10a"},
  61         {  1,           "R3.50a"},
  62         {  0xFF,        NULL   }
  63 };
  64
  65 static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
  66 {
  67         if (is_isa_arcompact()) {
  68                 struct bcr_iccm_arcompact iccm;
  69                 struct bcr_dccm_arcompact dccm;
  70
  71                 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
  72                 if (iccm.ver) {
  73                         cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */
  74                         cpu->iccm.base_addr = iccm.base << 16;
  75                 }
  76
  77                 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
  78                 if (dccm.ver) {
  79                         unsigned long base;
  80                         cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */
  81
  82                         base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD);
  83                         cpu->dccm.base_addr = base & ~0xF;
  84                 }
  85         } else {
  86                 struct bcr_iccm_arcv2 iccm;
  87                 struct bcr_dccm_arcv2 dccm;
  88                 unsigned long region;
  89
  90                 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
  91                 if (iccm.ver) {
  92                         cpu->iccm.sz = 256 << iccm.sz00;        /* 512B to 16M */
  93                         if (iccm.sz00 == 0xF && iccm.sz01 > 0)
  94                                 cpu->iccm.sz <<= iccm.sz01;
  95
  96                         region = read_aux_reg(ARC_REG_AUX_ICCM);
  97                         cpu->iccm.base_addr = region & 0xF0000000;
  98                 }
  99
 100                 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
 101                 if (dccm.ver) {
 102                         cpu->dccm.sz = 256 << dccm.sz0;
 103                         if (dccm.sz0 == 0xF && dccm.sz1 > 0)
 104                                 cpu->dccm.sz <<= dccm.sz1;
 105
 106                         region = read_aux_reg(ARC_REG_AUX_DCCM);
 107                         cpu->dccm.base_addr = region & 0xF0000000;
 108                 }
 109         }
 110 }
 111
 112 static void decode_arc_core(struct cpuinfo_arc *cpu)
 113 {
 114         struct bcr_uarch_build_arcv2 uarch;
 115         const struct id_to_str *tbl;
 116
 117         /*
 118          * Up until (including) the first core4 release (0x54) things were
 119          * simple: AUX IDENTITY.ARCVER was sufficient to identify arc family
 120          * and release: 0x50 to 0x53 was HS38, 0x54 was HS48 (dual issue)
 121          */
 122
 123         if (cpu->core.family < 0x54) { /* includes arc700 */
 124
 125                 for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) {
 126                         if (cpu->core.family == tbl->id) {
 127                                 cpu->release = tbl->str;
 128                                 break;
 129                         }
 130                 }
 131
 132                 if (is_isa_arcompact())
 133                         cpu->name = "ARC700";
 134                 else if (tbl->str)
 135                         cpu->name = "HS38";
 136                 else
 137                         cpu->name = cpu->release = "Unknown";
 138
 139                 return;
 140         }
 141
 142         /*
 143          * However the subsequent HS release (same 0x54) allow HS38 or HS48
 144          * configurations and encode this info in a different BCR.
 145          * The BCR was introduced in 0x54 so can't be read unconditionally.
 146          */
 147
 148         READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
 149
 150         if (uarch.prod == 4) {
 151                 cpu->name = "HS48";
 152                 cpu->extn.dual = 1;
 153
 154         } else {
 155                 cpu->name = "HS38";
 156         }
 157
 158         for (tbl = &arc_cpu_rel[0]; tbl->id != 0xFF; tbl++) {
 159                 if (uarch.maj == tbl->id) {
 160                         cpu->release = tbl->str;
 161                         break;
 162                 }
 163         }
 164 }
 165
 166 static void read_arc_build_cfg_regs(void)
 167 {
 168         struct bcr_timer timer;
 169         struct bcr_generic bcr;
 170         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
 171         struct bcr_isa_arcv2 isa;
 172         struct bcr_actionpoint ap;
 173
 174         FIX_PTR(cpu);
 175
 176         READ_BCR(AUX_IDENTITY, cpu->core);
 177         decode_arc_core(cpu);
 178
 179         READ_BCR(ARC_REG_TIMERS_BCR, timer);
 180         cpu->extn.timer0 = timer.t0;
 181         cpu->extn.timer1 = timer.t1;
 182         cpu->extn.rtc = timer.rtc;
 183
 184         cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
 185
 186         READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
 187
 188         /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
 189         read_decode_ccm_bcr(cpu);
 190
 191         read_decode_mmu_bcr();
 192         read_decode_cache_bcr();
 193
 194         if (is_isa_arcompact()) {
 195                 struct bcr_fp_arcompact sp, dp;
 196                 struct bcr_bpu_arcompact bpu;
 197
 198                 READ_BCR(ARC_REG_FP_BCR, sp);
 199                 READ_BCR(ARC_REG_DPFP_BCR, dp);
 200                 cpu->extn.fpu_sp = sp.ver ? 1 : 0;
 201                 cpu->extn.fpu_dp = dp.ver ? 1 : 0;
 202
 203                 READ_BCR(ARC_REG_BPU_BCR, bpu);
 204                 cpu->bpu.ver = bpu.ver;
 205                 cpu->bpu.full = bpu.fam ? 1 : 0;
 206                 if (bpu.ent) {
 207                         cpu->bpu.num_cache = 256 << (bpu.ent - 1);
 208                         cpu->bpu.num_pred = 256 << (bpu.ent - 1);
 209                 }
 210         } else {
 211                 struct bcr_fp_arcv2 spdp;
 212                 struct bcr_bpu_arcv2 bpu;
 213
 214                 READ_BCR(ARC_REG_FP_V2_BCR, spdp);
 215                 cpu->extn.fpu_sp = spdp.sp ? 1 : 0;
 216                 cpu->extn.fpu_dp = spdp.dp ? 1 : 0;
 217
 218                 READ_BCR(ARC_REG_BPU_BCR, bpu);
 219                 cpu->bpu.ver = bpu.ver;
 220                 cpu->bpu.full = bpu.ft;
 221                 cpu->bpu.num_cache = 256 << bpu.bce;
 222                 cpu->bpu.num_pred = 2048 << bpu.pte;
 223                 cpu->bpu.ret_stk = 4 << bpu.rse;
 224
 225                 /* if dual issue hardware, is it enabled ? */
 226                 if (cpu->extn.dual) {
 227                         unsigned int exec_ctrl;
 228
 229                         READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
 230                         cpu->extn.dual_enb = !(exec_ctrl & 1);
 231                 }
 232         }
 233
 234         READ_BCR(ARC_REG_AP_BCR, ap);
 235         if (ap.ver) {
 236                 cpu->extn.ap_num = 2 << ap.num;
 237                 cpu->extn.ap_full = !ap.min;
 238         }
 239
 240         READ_BCR(ARC_REG_SMART_BCR, bcr);
 241         cpu->extn.smart = bcr.ver ? 1 : 0;
 242
 243         READ_BCR(ARC_REG_RTT_BCR, bcr);
 244         cpu->extn.rtt = bcr.ver ? 1 : 0;
 245
 246         READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
 247
 248         /* some hacks for lack of feature BCR info in old ARC700 cores */
 249         if (is_isa_arcompact()) {
 250                 if (!isa.ver)   /* ISA BCR absent, use Kconfig info */
 251                         cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
 252                 else {
 253                         /* ARC700_BUILD only has 2 bits of isa info */
 254                         struct bcr_generic bcr = *(struct bcr_generic *)&isa;
 255                         cpu->isa.atomic = bcr.info & 1;
 256                 }
 257
 258                 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
 259
 260                  /* there's no direct way to distinguish 750 vs. 770 */
 261                 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
 262                         cpu->name = "ARC750";
 263         } else {
 264                 cpu->isa = isa;
 265         }
 266 }
 267
 268 static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
 269 {
 270         struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
 271         struct bcr_identity *core = &cpu->core;
 272         char mpy_opt[16];
 273         int n = 0;
 274
 275         FIX_PTR(cpu);
 276
 277         n += scnprintf(buf + n, len - n,
 278                        "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
 279                        core->family, core->cpu_id, core->chip_id);
 280
 281         n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
 282                        cpu_id, cpu->name, cpu->release,
 283                        is_isa_arcompact() ? "ARCompact" : "ARCv2",
 284                        IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
 285                        IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue "));
 286
 287         n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
 288                        IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
 289                        IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
 290                        IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT),
 291                        IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT));
 292
 293         if (cpu->extn_mpy.ver) {
 294                 if (is_isa_arcompact()) {
 295                         scnprintf(mpy_opt, 16, "mpy");
 296                 } else {
 297
 298                         int opt = 2;    /* stock MPY/MPYH */
 299
 300                         if (cpu->extn_mpy.dsp)  /* OPT 7-9 */
 301                                 opt = cpu->extn_mpy.dsp + 6;
 302
 303                         scnprintf(mpy_opt, 16, "mpy[opt %d] ", opt);
 304                 }
 305         }
 306
 307         n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
 308                        IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
 309                        IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
 310                        IS_AVAIL2(cpu->isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS),
 311                        IS_AVAIL1(cpu->extn_mpy.ver, mpy_opt),
 312                        IS_AVAIL1(cpu->isa.div_rem, "div_rem "));
 313
 314         if (cpu->bpu.ver) {
 315                 n += scnprintf(buf + n, len - n,
 316                               "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d",
 317                               IS_AVAIL1(cpu->bpu.full, "full"),
 318                               IS_AVAIL1(!cpu->bpu.full, "partial"),
 319                               cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk);
 320
 321                 if (is_isa_arcv2()) {
 322                         struct bcr_lpb lpb;
 323
 324                         READ_BCR(ARC_REG_LPB_BUILD, lpb);
 325                         if (lpb.ver) {
 326                                 unsigned int ctl;
 327                                 ctl = read_aux_reg(ARC_REG_LPB_CTRL);
 328
 329                                 n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s",
 330                                                lpb.entries,
 331                                                IS_DISABLED_RUN(!ctl));
 332                         }
 333                 }
 334                 n += scnprintf(buf + n, len - n, "\n");
 335         }
 336
 337         return buf;
 338 }
 339
 340 static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
 341 {
 342         int n = 0;
 343         struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
 344
 345         FIX_PTR(cpu);
 346
 347         n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base);
 348
 349         if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
 350                 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
 351                                IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
 352                                IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
 353
 354         if (cpu->extn.ap_num | cpu->extn.smart | cpu->extn.rtt) {
 355                 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s",
 356                                IS_AVAIL1(cpu->extn.smart, "smaRT "),
 357                                IS_AVAIL1(cpu->extn.rtt, "RTT "));
 358                 if (cpu->extn.ap_num) {
 359                         n += scnprintf(buf + n, len - n, "ActionPoint %d/%s",
 360                                        cpu->extn.ap_num,
 361                                        cpu->extn.ap_full ? "full":"min");
 362                 }
 363                 n += scnprintf(buf + n, len - n, "\n");
 364         }
 365
 366         if (cpu->dccm.sz || cpu->iccm.sz)
 367                 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
 368                                cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
 369                                cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
 370
 371         if (is_isa_arcv2()) {
 372
 373                 /* Error Protection: ECC/Parity */
 374                 struct bcr_erp erp;
 375                 READ_BCR(ARC_REG_ERP_BUILD, erp);
 376
 377                 if (erp.ver) {
 378                         struct  ctl_erp ctl;
 379                         READ_BCR(ARC_REG_ERP_CTRL, ctl);
 380
 381                         /* inverted bits: 0 means enabled */
 382                         n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n",
 383                                 IS_AVAIL3(erp.ic,  !ctl.dpi, "IC "),
 384                                 IS_AVAIL3(erp.dc,  !ctl.dpd, "DC "),
 385                                 IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU "));
 386                 }
 387         }
 388
 389         return buf;
 390 }
 391
 392 static void arc_chk_core_config(void)
 393 {
 394         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
 395         int saved = 0, present = 0;
 396         char *opt_nm = NULL;
 397
 398         if (!cpu->extn.timer0)
 399                 panic("Timer0 is not present!\n");
 400
 401         if (!cpu->extn.timer1)
 402                 panic("Timer1 is not present!\n");
 403
 404 #ifdef CONFIG_ARC_HAS_DCCM
 405         /*
 406          * DCCM can be arbit placed in hardware.
 407          * Make sure it's placement/sz matches what Linux is built with
 408          */
 409         if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
 410                 panic("Linux built with incorrect DCCM Base address\n");
 411
 412         if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz)
 413                 panic("Linux built with incorrect DCCM Size\n");
 414 #endif
 415
 416 #ifdef CONFIG_ARC_HAS_ICCM
 417         if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz)
 418                 panic("Linux built with incorrect ICCM Size\n");
 419 #endif
 420
 421         /*
 422          * FP hardware/software config sanity
 423          * -If hardware present, kernel needs to save/restore FPU state
 424          * -If not, it will crash trying to save/restore the non-existant regs
 425          */
 426
 427         if (is_isa_arcompact()) {
 428                 opt_nm = "CONFIG_ARC_FPU_SAVE_RESTORE";
 429                 saved = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);
 430
 431                 /* only DPDP checked since SP has no arch visible regs */
 432                 present = cpu->extn.fpu_dp;
 433         } else {
 434                 opt_nm = "CONFIG_ARC_HAS_ACCL_REGS";
 435                 saved = IS_ENABLED(CONFIG_ARC_HAS_ACCL_REGS);
 436
 437                 /* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */
 438                 present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp;
 439         }
 440
 441         if (present && !saved)
 442                 pr_warn("Enable %s for working apps\n", opt_nm);
 443         else if (!present && saved)
 444                 panic("Disable %s, hardware NOT present\n", opt_nm);
 445 }
 446
 447 /*
 448  * Initialize and setup the processor core
 449  * This is called by all the CPUs thus should not do special case stuff
 450  *    such as only for boot CPU etc
 451  */
 452
 453 void setup_processor(void)
 454 {
 455         char str[512];
 456         int cpu_id = smp_processor_id();
 457
 458         read_arc_build_cfg_regs();
 459         arc_init_IRQ();
 460
 461         pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
 462
 463         arc_mmu_init();
 464         arc_cache_init();
 465
 466         pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
 467         pr_info("%s", arc_platform_smp_cpuinfo());
 468
 469         arc_chk_core_config();
 470 }
 471
 472 static inline bool uboot_arg_invalid(unsigned long addr)
 473 {
 474         /*
 475          * Check that it is a untranslated address (although MMU is not enabled
 476          * yet, it being a high address ensures this is not by fluke)
 477          */
 478         if (addr < PAGE_OFFSET)
 479                 return true;
 480
 481         /* Check that address doesn't clobber resident kernel image */
 482         return addr >= (unsigned long)_stext && addr <= (unsigned long)_end;
 483 }
 484
 485 #define IGNORE_ARGS             "Ignore U-boot args: "
 486
 487 /* uboot_tag values for U-boot - kernel ABI revision 0; see head.S */
 488 #define UBOOT_TAG_NONE          0
 489 #define UBOOT_TAG_CMDLINE       1
 490 #define UBOOT_TAG_DTB           2
 491 /* We always pass 0 as magic from U-boot */
 492 #define UBOOT_MAGIC_VALUE       0
 493
 494 void __init handle_uboot_args(void)
 495 {
 496         bool use_embedded_dtb = true;
 497         bool append_cmdline = false;
 498
 499         /* check that we know this tag */
 500         if (uboot_tag != UBOOT_TAG_NONE &&
 501             uboot_tag != UBOOT_TAG_CMDLINE &&
 502             uboot_tag != UBOOT_TAG_DTB) {
 503                 pr_warn(IGNORE_ARGS "invalid uboot tag: '%08x'\n", uboot_tag);
 504                 goto ignore_uboot_args;
 505         }
 506
 507         if (uboot_magic != UBOOT_MAGIC_VALUE) {
 508                 pr_warn(IGNORE_ARGS "non zero uboot magic\n");
 509                 goto ignore_uboot_args;
 510         }
 511
 512         if (uboot_tag != UBOOT_TAG_NONE &&
 513             uboot_arg_invalid((unsigned long)uboot_arg)) {
 514                 pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg);
 515                 goto ignore_uboot_args;
 516         }
 517
 518         /* see if U-boot passed an external Device Tree blob */
 519         if (uboot_tag == UBOOT_TAG_DTB) {
 520                 machine_desc = setup_machine_fdt((void *)uboot_arg);
 521
 522                 /* external Device Tree blob is invalid - use embedded one */
 523                 use_embedded_dtb = !machine_desc;
 524         }
 525
 526         if (uboot_tag == UBOOT_TAG_CMDLINE)
 527                 append_cmdline = true;
 528
 529 ignore_uboot_args:
 530
 531         if (use_embedded_dtb) {
 532                 machine_desc = setup_machine_fdt(__dtb_start);
 533                 if (!machine_desc)
 534                         panic("Embedded DT invalid\n");
 535         }
 536
 537         /*
 538          * NOTE: @boot_command_line is populated by setup_machine_fdt() so this
 539          * append processing can only happen after.
 540          */
 541         if (append_cmdline) {
 542                 /* Ensure a whitespace between the 2 cmdlines */
 543                 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
 544                 strlcat(boot_command_line, uboot_arg, COMMAND_LINE_SIZE);
 545         }
 546 }
 547
 548 void __init setup_arch(char **cmdline_p)
 549 {
 550         handle_uboot_args();
 551
 552         /* Save unparsed command line copy for /proc/cmdline */
 553         *cmdline_p = boot_command_line;
 554
 555         /* To force early parsing of things like mem=xxx */
 556         parse_early_param();
 557
 558         /* Platform/board specific: e.g. early console registration */
 559         if (machine_desc->init_early)
 560                 machine_desc->init_early();
 561
 562         smp_init_cpus();
 563
 564         setup_processor();
 565         setup_arch_memory();
 566
 567         /* copy flat DT out of .init and then unflatten it */
 568         unflatten_and_copy_device_tree();
 569
 570         /* Can be issue if someone passes cmd line arg "ro"
 571          * But that is unlikely so keeping it as it is
 572          */
 573         root_mountflags &= ~MS_RDONLY;
 574
 575         arc_unwind_init();
 576 }
 577
 578 /*
 579  * Called from start_kernel() - boot CPU only
 580  */
 581 void __init time_init(void)
 582 {
 583         of_clk_init(NULL);
 584         timer_probe();
 585 }
 586
 587 static int __init customize_machine(void)
 588 {
 589         if (machine_desc->init_machine)
 590                 machine_desc->init_machine();
 591
 592         return 0;
 593 }
 594 arch_initcall(customize_machine);
 595
 596 static int __init init_late_machine(void)
 597 {
 598         if (machine_desc->init_late)
 599                 machine_desc->init_late();
 600
 601         return 0;
 602 }
 603 late_initcall(init_late_machine);
 604 /*
 605  *  Get CPU information for use by the procfs.
 606  */
 607
 608 #define cpu_to_ptr(c)   ((void *)(0xFFFF0000 | (unsigned int)(c)))
 609 #define ptr_to_cpu(p)   (~0xFFFF0000UL & (unsigned int)(p))
 610
 611 static int show_cpuinfo(struct seq_file *m, void *v)
 612 {
 613         char *str;
 614         int cpu_id = ptr_to_cpu(v);
 615         struct device *cpu_dev = get_cpu_device(cpu_id);
 616         struct clk *cpu_clk;
 617         unsigned long freq = 0;
 618
 619         if (!cpu_online(cpu_id)) {
 620                 seq_printf(m, "processor [%d]\t: Offline\n", cpu_id);
 621                 goto done;
 622         }
 623
 624         str = (char *)__get_free_page(GFP_KERNEL);
 625         if (!str)
 626                 goto done;
 627
 628         seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
 629
 630         cpu_clk = clk_get(cpu_dev, NULL);
 631         if (IS_ERR(cpu_clk)) {
 632                 seq_printf(m, "CPU speed \t: Cannot get clock for processor [%d]\n",
 633                            cpu_id);
 634         } else {
 635                 freq = clk_get_rate(cpu_clk);
 636         }
 637         if (freq)
 638                 seq_printf(m, "CPU speed\t: %lu.%02lu Mhz\n",
 639                            freq / 1000000, (freq / 10000) % 100);
 640
 641         seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
 642                    loops_per_jiffy / (500000 / HZ),
 643                    (loops_per_jiffy / (5000 / HZ)) % 100);
 644
 645         seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
 646         seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
 647         seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
 648         seq_printf(m, arc_platform_smp_cpuinfo());
 649
 650         free_page((unsigned long)str);
 651 done:
 652         seq_printf(m, "\n");
 653
 654         return 0;
 655 }
 656
 657 static void *c_start(struct seq_file *m, loff_t *pos)
 658 {
 659         /*
 660          * Callback returns cpu-id to iterator for show routine, NULL to stop.
 661          * However since NULL is also a valid cpu-id (0), we use a round-about
 662          * way to pass it w/o having to kmalloc/free a 2 byte string.
 663          * Encode cpu-id as 0xFFcccc, which is decoded by show routine.
 664          */
 665         return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
 666 }
 667
 668 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 669 {
 670         ++*pos;
 671         return c_start(m, pos);
 672 }
 673
 674 static void c_stop(struct seq_file *m, void *v)
 675 {
 676 }
 677
 678 const struct seq_operations cpuinfo_op = {
 679         .start  = c_start,
 680         .next   = c_next,
 681         .stop   = c_stop,
 682         .show   = show_cpuinfo
 683 };
 684
 685 static DEFINE_PER_CPU(struct cpu, cpu_topology);
 686
 687 static int __init topology_init(void)
 688 {
 689         int cpu;
 690
 691         for_each_present_cpu(cpu)
 692             register_cpu(&per_cpu(cpu_topology, cpu), cpu);
 693
 694         return 0;
 695 }
 696
 697 subsys_initcall(topology_init);