| blob | 646f11430dadbc2c3d70e853e4566686035ac607 |
1 /*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/am33xx.h>
14 #include <dt-bindings/clock/am3.h>
16 / {
17 compatible = "ti,am33xx";
18 interrupt-parent = <&intc>;
19 #address-cells = <1>;
20 #size-cells = <1>;
21 chosen { };
23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 serial2 = &uart2;
30 serial3 = &uart3;
31 serial4 = &uart4;
32 serial5 = &uart5;
33 d-can0 = &dcan0;
34 d-can1 = &dcan1;
35 usb0 = &usb0;
36 usb1 = &usb1;
37 phy0 = &usb0_phy;
38 phy1 = &usb1_phy;
39 ethernet0 = &cpsw_emac0;
40 ethernet1 = &cpsw_emac1;
41 spi0 = &spi0;
42 spi1 = &spi1;
43 };
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cpu@0 {
49 compatible = "arm,cortex-a8";
50 device_type = "cpu";
51 reg = <0>;
53 operating-points-v2 = <&cpu0_opp_table>;
55 clocks = <&dpll_mpu_ck>;
56 clock-names = "cpu";
58 clock-latency = <300000>; /* From omap-cpufreq driver */
59 };
60 };
62 cpu0_opp_table: opp-table {
63 compatible = "operating-points-v2-ti-cpu";
64 syscon = <&scm_conf>;
66 /*
67 * The three following nodes are marked with opp-suspend
68 * because the can not be enabled simultaneously on a
69 * single SoC.
70 */
71 opp50-300000000 {
72 opp-hz = /bits/ 64 <300000000>;
73 opp-microvolt = <950000 931000 969000>;
74 opp-supported-hw = <0x06 0x0010>;
75 opp-suspend;
76 };
78 opp100-275000000 {
79 opp-hz = /bits/ 64 <275000000>;
80 opp-microvolt = <1100000 1078000 1122000>;
81 opp-supported-hw = <0x01 0x00FF>;
82 opp-suspend;
83 };
85 opp100-300000000 {
86 opp-hz = /bits/ 64 <300000000>;
87 opp-microvolt = <1100000 1078000 1122000>;
88 opp-supported-hw = <0x06 0x0020>;
89 opp-suspend;
90 };
92 opp100-500000000 {
93 opp-hz = /bits/ 64 <500000000>;
94 opp-microvolt = <1100000 1078000 1122000>;
95 opp-supported-hw = <0x01 0xFFFF>;
96 };
98 opp100-600000000 {
99 opp-hz = /bits/ 64 <600000000>;
100 opp-microvolt = <1100000 1078000 1122000>;
101 opp-supported-hw = <0x06 0x0040>;
102 };
104 opp120-600000000 {
105 opp-hz = /bits/ 64 <600000000>;
106 opp-microvolt = <1200000 1176000 1224000>;
107 opp-supported-hw = <0x01 0xFFFF>;
108 };
110 opp120-720000000 {
111 opp-hz = /bits/ 64 <720000000>;
112 opp-microvolt = <1200000 1176000 1224000>;
113 opp-supported-hw = <0x06 0x0080>;
114 };
116 oppturbo-720000000 {
117 opp-hz = /bits/ 64 <720000000>;
118 opp-microvolt = <1260000 1234800 1285200>;
119 opp-supported-hw = <0x01 0xFFFF>;
120 };
122 oppturbo-800000000 {
123 opp-hz = /bits/ 64 <800000000>;
124 opp-microvolt = <1260000 1234800 1285200>;
125 opp-supported-hw = <0x06 0x0100>;
126 };
128 oppnitro-1000000000 {
129 opp-hz = /bits/ 64 <1000000000>;
130 opp-microvolt = <1325000 1298500 1351500>;
131 opp-supported-hw = <0x04 0x0200>;
132 };
133 };
135 pmu@4b000000 {
136 compatible = "arm,cortex-a8-pmu";
137 interrupts = <3>;
138 reg = <0x4b000000 0x1000000>;
139 ti,hwmods = "debugss";
140 };
142 /*
143 * The soc node represents the soc top level view. It is used for IPs
144 * that are not memory mapped in the MPU view or for the MPU itself.
145 */
146 soc {
147 compatible = "ti,omap-infra";
148 mpu {
149 compatible = "ti,omap3-mpu";
150 ti,hwmods = "mpu";
151 pm-sram = <&pm_sram_code
152 &pm_sram_data>;
153 };
154 };
156 /*
157 * XXX: Use a flat representation of the AM33XX interconnect.
158 * The real AM33XX interconnect network is quite complex. Since
159 * it will not bring real advantage to represent that in DT
160 * for the moment, just use a fake OCP bus entry to represent
161 * the whole bus hierarchy.
162 */
163 ocp {
164 compatible = "simple-bus";
165 #address-cells = <1>;
166 #size-cells = <1>;
167 ranges;
168 ti,hwmods = "l3_main";
170 l4_wkup: interconnect@44c00000 {
171 wkup_m3: wkup_m3@100000 {
172 compatible = "ti,am3352-wkup-m3";
173 reg = <0x100000 0x4000>,
174 <0x180000 0x2000>;
175 reg-names = "umem", "dmem";
176 ti,hwmods = "wkup_m3";
177 ti,pm-firmware = "am335x-pm-firmware.elf";
178 };
179 };
180 l4_per: interconnect@48000000 {
181 };
182 l4_fw: interconnect@47c00000 {
183 };
184 l4_fast: interconnect@4a000000 {
185 };
186 l4_mpuss: interconnect@4b140000 {
187 };
189 intc: interrupt-controller@48200000 {
190 compatible = "ti,am33xx-intc";
191 interrupt-controller;
192 #interrupt-cells = <1>;
193 reg = <0x48200000 0x1000>;
194 };
196 edma: edma@49000000 {
197 compatible = "ti,edma3-tpcc";
198 ti,hwmods = "tpcc";
199 reg = <0x49000000 0x10000>;
200 reg-names = "edma3_cc";
201 interrupts = <12 13 14>;
202 interrupt-names = "edma3_ccint", "edma3_mperr",
203 "edma3_ccerrint";
204 dma-requests = <64>;
205 #dma-cells = <2>;
207 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
208 <&edma_tptc2 0>;
210 ti,edma-memcpy-channels = <20 21>;
211 };
213 edma_tptc0: tptc@49800000 {
214 compatible = "ti,edma3-tptc";
215 ti,hwmods = "tptc0";
216 reg = <0x49800000 0x100000>;
217 interrupts = <112>;
218 interrupt-names = "edma3_tcerrint";
219 };
221 edma_tptc1: tptc@49900000 {
222 compatible = "ti,edma3-tptc";
223 ti,hwmods = "tptc1";
224 reg = <0x49900000 0x100000>;
225 interrupts = <113>;
226 interrupt-names = "edma3_tcerrint";
227 };
229 edma_tptc2: tptc@49a00000 {
230 compatible = "ti,edma3-tptc";
231 ti,hwmods = "tptc2";
232 reg = <0x49a00000 0x100000>;
233 interrupts = <114>;
234 interrupt-names = "edma3_tcerrint";
235 };
237 target-module@47810000 {
238 compatible = "ti,sysc-omap2", "ti,sysc";
239 reg = <0x478102fc 0x4>,
240 <0x47810110 0x4>,
241 <0x47810114 0x4>;
242 reg-names = "rev", "sysc", "syss";
243 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
244 SYSC_OMAP2_ENAWAKEUP |
245 SYSC_OMAP2_SOFTRESET |
246 SYSC_OMAP2_AUTOIDLE)>;
247 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
248 <SYSC_IDLE_NO>,
249 <SYSC_IDLE_SMART>;
250 ti,syss-mask = <1>;
251 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
252 clock-names = "fck";
253 #address-cells = <1>;
254 #size-cells = <1>;
255 ranges = <0x0 0x47810000 0x1000>;
257 mmc3: mmc@0 {
258 compatible = "ti,omap4-hsmmc";
259 ti,needs-special-reset;
260 interrupts = <29>;
261 reg = <0x0 0x1000>;
262 };
263 };
265 usb: target-module@47400000 {
266 compatible = "ti,sysc-omap4", "ti,sysc";
267 reg = <0x47400000 0x4>,
268 <0x47400010 0x4>;
269 reg-names = "rev", "sysc";
270 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
271 SYSC_OMAP2_SOFTRESET)>;
272 ti,sysc-midle = <SYSC_IDLE_FORCE>,
273 <SYSC_IDLE_NO>,
274 <SYSC_IDLE_SMART>;
275 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
276 <SYSC_IDLE_NO>,
277 <SYSC_IDLE_SMART>,
278 <SYSC_IDLE_SMART_WKUP>;
279 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
280 clock-names = "fck";
281 #address-cells = <1>;
282 #size-cells = <1>;
283 ranges = <0x0 0x47400000 0x5000>;
285 usb0_phy: usb-phy@1300 {
286 compatible = "ti,am335x-usb-phy";
287 reg = <0x1300 0x100>;
288 reg-names = "phy";
289 ti,ctrl_mod = <&usb_ctrl_mod>;
290 #phy-cells = <0>;
291 };
293 usb0: usb@1400 {
294 compatible = "ti,musb-am33xx";
295 reg = <0x1400 0x400>,
296 <0x1000 0x200>;
297 reg-names = "mc", "control";
299 interrupts = <18>;
300 interrupt-names = "mc";
301 dr_mode = "otg";
302 mentor,multipoint = <1>;
303 mentor,num-eps = <16>;
304 mentor,ram-bits = <12>;
305 mentor,power = <500>;
306 phys = <&usb0_phy>;
308 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
309 &cppi41dma 2 0 &cppi41dma 3 0
310 &cppi41dma 4 0 &cppi41dma 5 0
311 &cppi41dma 6 0 &cppi41dma 7 0
312 &cppi41dma 8 0 &cppi41dma 9 0
313 &cppi41dma 10 0 &cppi41dma 11 0
314 &cppi41dma 12 0 &cppi41dma 13 0
315 &cppi41dma 14 0 &cppi41dma 0 1
316 &cppi41dma 1 1 &cppi41dma 2 1
317 &cppi41dma 3 1 &cppi41dma 4 1
318 &cppi41dma 5 1 &cppi41dma 6 1
319 &cppi41dma 7 1 &cppi41dma 8 1
320 &cppi41dma 9 1 &cppi41dma 10 1
321 &cppi41dma 11 1 &cppi41dma 12 1
322 &cppi41dma 13 1 &cppi41dma 14 1>;
323 dma-names =
324 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
325 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
326 "rx14", "rx15",
327 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
328 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
329 "tx14", "tx15";
330 };
332 usb1_phy: usb-phy@1b00 {
333 compatible = "ti,am335x-usb-phy";
334 reg = <0x1b00 0x100>;
335 reg-names = "phy";
336 ti,ctrl_mod = <&usb_ctrl_mod>;
337 #phy-cells = <0>;
338 };
340 usb1: usb@1800 {
341 compatible = "ti,musb-am33xx";
342 reg = <0x1c00 0x400>,
343 <0x1800 0x200>;
344 reg-names = "mc", "control";
345 interrupts = <19>;
346 interrupt-names = "mc";
347 dr_mode = "otg";
348 mentor,multipoint = <1>;
349 mentor,num-eps = <16>;
350 mentor,ram-bits = <12>;
351 mentor,power = <500>;
352 phys = <&usb1_phy>;
354 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
355 &cppi41dma 17 0 &cppi41dma 18 0
356 &cppi41dma 19 0 &cppi41dma 20 0
357 &cppi41dma 21 0 &cppi41dma 22 0
358 &cppi41dma 23 0 &cppi41dma 24 0
359 &cppi41dma 25 0 &cppi41dma 26 0
360 &cppi41dma 27 0 &cppi41dma 28 0
361 &cppi41dma 29 0 &cppi41dma 15 1
362 &cppi41dma 16 1 &cppi41dma 17 1
363 &cppi41dma 18 1 &cppi41dma 19 1
364 &cppi41dma 20 1 &cppi41dma 21 1
365 &cppi41dma 22 1 &cppi41dma 23 1
366 &cppi41dma 24 1 &cppi41dma 25 1
367 &cppi41dma 26 1 &cppi41dma 27 1
368 &cppi41dma 28 1 &cppi41dma 29 1>;
369 dma-names =
370 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
371 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
372 "rx14", "rx15",
373 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
374 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
375 "tx14", "tx15";
376 };
378 cppi41dma: dma-controller@2000 {
379 compatible = "ti,am3359-cppi41";
380 reg = <0x0000 0x1000>,
381 <0x2000 0x1000>,
382 <0x3000 0x1000>,
383 <0x4000 0x4000>;
384 reg-names = "glue", "controller", "scheduler", "queuemgr";
385 interrupts = <17>;
386 interrupt-names = "glue";
387 #dma-cells = <2>;
388 #dma-channels = <30>;
389 #dma-requests = <256>;
390 };
391 };
393 ocmcram: sram@40300000 {
394 compatible = "mmio-sram";
395 reg = <0x40300000 0x10000>; /* 64k */
396 ranges = <0x0 0x40300000 0x10000>;
397 #address-cells = <1>;
398 #size-cells = <1>;
400 pm_sram_code: pm-code-sram@0 {
401 compatible = "ti,sram";
402 reg = <0x0 0x1000>;
403 protect-exec;
404 };
406 pm_sram_data: pm-data-sram@1000 {
407 compatible = "ti,sram";
408 reg = <0x1000 0x1000>;
409 pool;
410 };
411 };
413 emif: emif@4c000000 {
414 compatible = "ti,emif-am3352";
415 reg = <0x4c000000 0x1000000>;
416 ti,hwmods = "emif";
417 interrupts = <101>;
418 sram = <&pm_sram_code
419 &pm_sram_data>;
420 ti,no-idle;
421 };
423 gpmc: gpmc@50000000 {
424 compatible = "ti,am3352-gpmc";
425 ti,hwmods = "gpmc";
426 ti,no-idle-on-init;
427 reg = <0x50000000 0x2000>;
428 interrupts = <100>;
429 dmas = <&edma 52 0>;
430 dma-names = "rxtx";
431 gpmc,num-cs = <7>;
432 gpmc,num-waitpins = <2>;
433 #address-cells = <2>;
434 #size-cells = <1>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
437 gpio-controller;
438 #gpio-cells = <2>;
439 status = "disabled";
440 };
442 sham: sham@53100000 {
443 compatible = "ti,omap4-sham";
444 ti,hwmods = "sham";
445 reg = <0x53100000 0x200>;
446 interrupts = <109>;
447 dmas = <&edma 36 0>;
448 dma-names = "rx";
449 };
451 aes: aes@53500000 {
452 compatible = "ti,omap4-aes";
453 ti,hwmods = "aes";
454 reg = <0x53500000 0xa0>;
455 interrupts = <103>;
456 dmas = <&edma 6 0>,
457 <&edma 5 0>;
458 dma-names = "tx", "rx";
459 };
460 };
461 };
463 #include "am33xx-l4.dtsi"
464 #include "am33xx-clocks.dtsi"
466 &prcm {
467 prm_per: prm@c00 {
468 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
469 reg = <0xc00 0x100>;
470 #reset-cells = <1>;
471 };
473 prm_wkup: prm@d00 {
474 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
475 reg = <0xd00 0x100>;
476 #reset-cells = <1>;
477 };
479 prm_device: prm@f00 {
480 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
481 reg = <0xf00 0x100>;
482 #reset-cells = <1>;
483 };
485 prm_gfx: prm@1100 {
486 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
487 reg = <0x1100 0x100>;
488 #reset-cells = <1>;
489 };
490 };