1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada XP family SoC
5 * Copyright (C) 2012 Marvell
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * Ben Dooks <ben.dooks@codethink.co.uk>
12 * Contains definitions specific to the Armada XP SoC that are not
13 * common to all Armada SoCs.
16 #include "armada-370-xp.dtsi"
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
34 compatible = "marvell,bootrom";
35 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
40 compatible = "marvell,armada-xp-sdram-controller";
45 compatible = "marvell,aurora-system-cache";
46 reg = <0x08000 0x1000>;
47 cache-id-part = <0x100>;
54 compatible = "snps,dw-apb-uart";
55 pinctrl-0 = <&uart2_pins>;
56 pinctrl-names = "default";
57 reg = <0x12200 0x100>;
61 clocks = <&coreclk 0>;
66 compatible = "snps,dw-apb-uart";
67 pinctrl-0 = <&uart3_pins>;
68 pinctrl-names = "default";
69 reg = <0x12300 0x100>;
73 clocks = <&coreclk 0>;
77 systemc: system-controller@18200 {
78 compatible = "marvell,armada-370-xp-system-controller";
79 reg = <0x18200 0x500>;
82 gateclk: clock-gating-control@18220 {
83 compatible = "marvell,armada-xp-gating-clock";
85 clocks = <&coreclk 0>;
89 coreclk: mvebu-sar@18230 {
90 compatible = "marvell,armada-xp-core-clock";
95 thermal: thermal@182b0 {
96 compatible = "marvell,armadaxp-thermal";
102 cpuclk: clock-complex@18700 {
104 compatible = "marvell,armada-xp-cpu-clock";
105 reg = <0x18700 0x24>, <0x1c054 0x10>;
106 clocks = <&coreclk 1>;
110 compatible = "marvell,armada-xp-cpu-config";
114 eth2: ethernet@30000 {
115 compatible = "marvell,armada-xp-neta";
116 reg = <0x30000 0x4000>;
118 clocks = <&gateclk 2>;
123 compatible = "marvell,orion-ehci";
124 reg = <0x52000 0x500>;
126 clocks = <&gateclk 20>;
131 compatible = "marvell,orion-xor";
134 clocks = <&gateclk 22>;
151 compatible = "marvell,armada-xp-neta";
155 compatible = "marvell,armada-xp-neta";
159 compatible = "marvell,armada-xp-crypto";
160 reg = <0x90000 0x10000>;
162 interrupts = <48>, <49>;
163 clocks = <&gateclk 23>, <&gateclk 23>;
164 clock-names = "cesa0", "cesa1";
165 marvell,crypto-srams = <&crypto_sram0>,
167 marvell,crypto-sram-size = <0x800>;
171 compatible = "marvell,armada-380-neta-bm";
172 reg = <0xc0000 0xac>;
173 clocks = <&gateclk 13>;
174 internal-mem = <&bm_bppi>;
179 compatible = "marvell,orion-xor";
182 clocks = <&gateclk 28>;
199 crypto_sram0: sa-sram0 {
200 compatible = "mmio-sram";
201 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
202 clocks = <&gateclk 23>;
203 #address-cells = <1>;
205 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
208 crypto_sram1: sa-sram1 {
209 compatible = "mmio-sram";
210 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
211 clocks = <&gateclk 23>;
212 #address-cells = <1>;
214 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
218 compatible = "mmio-sram";
219 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
220 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
221 #address-cells = <1>;
223 clocks = <&gateclk 13>;
230 /* 25 MHz reference crystal */
232 compatible = "fixed-clock";
234 clock-frequency = <25000000>;
240 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
241 reg = <0x11000 0x100>;
245 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
246 reg = <0x11100 0x100>;
250 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
254 compatible = "marvell,armada-xp-timer";
255 clocks = <&coreclk 2>, <&refclk>;
256 clock-names = "nbclk", "fixed";
260 compatible = "marvell,armada-xp-wdt";
261 clocks = <&coreclk 2>, <&refclk>;
262 clock-names = "nbclk", "fixed";
266 reg = <0x20800 0x20>;
270 clocks = <&gateclk 18>;
274 clocks = <&gateclk 19>;
278 ge0_gmii_pins: ge0-gmii-pins {
280 "mpp0", "mpp1", "mpp2", "mpp3",
281 "mpp4", "mpp5", "mpp6", "mpp7",
282 "mpp8", "mpp9", "mpp10", "mpp11",
283 "mpp12", "mpp13", "mpp14", "mpp15",
284 "mpp16", "mpp17", "mpp18", "mpp19",
285 "mpp20", "mpp21", "mpp22", "mpp23";
286 marvell,function = "ge0";
289 ge0_rgmii_pins: ge0-rgmii-pins {
291 "mpp0", "mpp1", "mpp2", "mpp3",
292 "mpp4", "mpp5", "mpp6", "mpp7",
293 "mpp8", "mpp9", "mpp10", "mpp11";
294 marvell,function = "ge0";
297 ge1_rgmii_pins: ge1-rgmii-pins {
299 "mpp12", "mpp13", "mpp14", "mpp15",
300 "mpp16", "mpp17", "mpp18", "mpp19",
301 "mpp20", "mpp21", "mpp22", "mpp23";
302 marvell,function = "ge1";
305 sdio_pins: sdio-pins {
306 marvell,pins = "mpp30", "mpp31", "mpp32",
307 "mpp33", "mpp34", "mpp35";
308 marvell,function = "sd0";
311 spi0_pins: spi0-pins {
312 marvell,pins = "mpp36", "mpp37",
314 marvell,function = "spi0";
317 spi1_pins: spi1-pins {
318 marvell,pins = "mpp13", "mpp14",
320 marvell,function = "spi1";
323 uart2_pins: uart2-pins {
324 marvell,pins = "mpp42", "mpp43";
325 marvell,function = "uart2";
328 uart3_pins: uart3-pins {
329 marvell,pins = "mpp44", "mpp45";
330 marvell,function = "uart3";
335 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
336 pinctrl-0 = <&spi0_pins>;
337 pinctrl-names = "default";
341 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
342 pinctrl-0 = <&spi1_pins>;
343 pinctrl-names = "default";