1 // SPDX-License-Identifier: GPL-2.0
2 #include "bcm283x.dtsi"
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
8 compatible = "brcm,bcm2711";
13 interrupt-parent = <&gicv2>;
21 * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
22 * that's not good enough for the BCM2711 as some devices can
23 * only address the lower 1G of memory (ZONE_DMA).
26 compatible = "shared-dma-pool";
27 size = <0x2000000>; /* 32MB */
28 alloc-ranges = <0x0 0x00000000 0x40000000>;
38 * Common BCM283x peripherals
39 * BCM2711-specific peripherals
40 * ARM-local peripherals
42 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
43 <0x7c000000 0x0 0xfc000000 0x02000000>,
44 <0x40000000 0x0 0xff800000 0x00800000>;
45 /* Emulate a contiguous 30-bit address range for DMA */
46 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
49 * This node is the provider for the enable-method for
50 * bringing up secondary cores.
52 local_intc: local_intc@40000000 {
53 compatible = "brcm,bcm2836-l1-intc";
54 reg = <0x40000000 0x100>;
57 gicv2: interrupt-controller@40041000 {
59 #interrupt-cells = <3>;
60 compatible = "arm,gic-400";
61 reg = <0x40041000 0x1000>,
65 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
66 IRQ_TYPE_LEVEL_HIGH)>;
69 avs_monitor: avs-monitor@7d5d2000 {
70 compatible = "brcm,bcm2711-avs-monitor",
71 "syscon", "simple-mfd";
72 reg = <0x7d5d2000 0xf00>;
75 compatible = "brcm,bcm2711-thermal";
76 #thermal-sensor-cells = <0>;
81 compatible = "brcm,bcm2835-dma";
82 reg = <0x7e007000 0xb00>;
83 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
95 interrupt-names = "dma0",
107 brcm,dma-channel-mask = <0x07f5>;
110 pm: watchdog@7e100000 {
111 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
112 #power-domain-cells = <1>;
114 reg = <0x7e100000 0x114>,
117 clocks = <&clocks BCM2835_CLOCK_V3D>,
118 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
119 <&clocks BCM2835_CLOCK_H264>,
120 <&clocks BCM2835_CLOCK_ISP>;
121 clock-names = "v3d", "peri_image", "h264", "isp";
122 system-power-controller;
126 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
128 /* RNG is incompatible with brcm,bcm2835-rng */
132 uart2: serial@7e201400 {
133 compatible = "arm,pl011", "arm,primecell";
134 reg = <0x7e201400 0x200>;
135 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&clocks BCM2835_CLOCK_UART>,
137 <&clocks BCM2835_CLOCK_VPU>;
138 clock-names = "uartclk", "apb_pclk";
139 arm,primecell-periphid = <0x00241011>;
143 uart3: serial@7e201600 {
144 compatible = "arm,pl011", "arm,primecell";
145 reg = <0x7e201600 0x200>;
146 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clocks BCM2835_CLOCK_UART>,
148 <&clocks BCM2835_CLOCK_VPU>;
149 clock-names = "uartclk", "apb_pclk";
150 arm,primecell-periphid = <0x00241011>;
154 uart4: serial@7e201800 {
155 compatible = "arm,pl011", "arm,primecell";
156 reg = <0x7e201800 0x200>;
157 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clocks BCM2835_CLOCK_UART>,
159 <&clocks BCM2835_CLOCK_VPU>;
160 clock-names = "uartclk", "apb_pclk";
161 arm,primecell-periphid = <0x00241011>;
165 uart5: serial@7e201a00 {
166 compatible = "arm,pl011", "arm,primecell";
167 reg = <0x7e201a00 0x200>;
168 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&clocks BCM2835_CLOCK_UART>,
170 <&clocks BCM2835_CLOCK_VPU>;
171 clock-names = "uartclk", "apb_pclk";
172 arm,primecell-periphid = <0x00241011>;
177 compatible = "brcm,bcm2835-spi";
178 reg = <0x7e204600 0x0200>;
179 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&clocks BCM2835_CLOCK_VPU>;
181 #address-cells = <1>;
187 compatible = "brcm,bcm2835-spi";
188 reg = <0x7e204800 0x0200>;
189 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&clocks BCM2835_CLOCK_VPU>;
191 #address-cells = <1>;
197 compatible = "brcm,bcm2835-spi";
198 reg = <0x7e204a00 0x0200>;
199 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&clocks BCM2835_CLOCK_VPU>;
201 #address-cells = <1>;
207 compatible = "brcm,bcm2835-spi";
208 reg = <0x7e204c00 0x0200>;
209 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clocks BCM2835_CLOCK_VPU>;
211 #address-cells = <1>;
217 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
218 reg = <0x7e205600 0x200>;
219 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&clocks BCM2835_CLOCK_VPU>;
221 #address-cells = <1>;
227 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
228 reg = <0x7e205800 0x200>;
229 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&clocks BCM2835_CLOCK_VPU>;
231 #address-cells = <1>;
237 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
238 reg = <0x7e205a00 0x200>;
239 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&clocks BCM2835_CLOCK_VPU>;
241 #address-cells = <1>;
247 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
248 reg = <0x7e205c00 0x200>;
249 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&clocks BCM2835_CLOCK_VPU>;
251 #address-cells = <1>;
257 compatible = "brcm,bcm2835-pwm";
258 reg = <0x7e20c800 0x28>;
259 clocks = <&clocks BCM2835_CLOCK_PWM>;
260 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
261 assigned-clock-rates = <10000000>;
266 emmc2: emmc2@7e340000 {
267 compatible = "brcm,bcm2711-emmc2";
268 reg = <0x7e340000 0x100>;
269 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clocks BCM2711_CLOCK_EMMC2>;
275 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
280 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
281 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
285 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
289 compatible = "arm,armv8-timer";
290 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
291 IRQ_TYPE_LEVEL_LOW)>,
292 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
293 IRQ_TYPE_LEVEL_LOW)>,
294 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
295 IRQ_TYPE_LEVEL_LOW)>,
296 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
297 IRQ_TYPE_LEVEL_LOW)>;
298 /* This only applies to the ARMv7 stub */
299 arm,cpu-registers-not-fw-configured;
303 #address-cells = <1>;
305 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
309 compatible = "arm,cortex-a72";
311 enable-method = "spin-table";
312 cpu-release-addr = <0x0 0x000000d8>;
317 compatible = "arm,cortex-a72";
319 enable-method = "spin-table";
320 cpu-release-addr = <0x0 0x000000e0>;
325 compatible = "arm,cortex-a72";
327 enable-method = "spin-table";
328 cpu-release-addr = <0x0 0x000000e8>;
333 compatible = "arm,cortex-a72";
335 enable-method = "spin-table";
336 cpu-release-addr = <0x0 0x000000f0>;
341 compatible = "simple-bus";
342 #address-cells = <2>;
345 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>;
347 genet: ethernet@7d580000 {
348 compatible = "brcm,bcm2711-genet-v5";
349 reg = <0x0 0x7d580000 0x10000>;
350 #address-cells = <0x1>;
352 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
356 genet_mdio: mdio@e14 {
357 compatible = "brcm,genet-mdio-v5";
360 #address-cells = <0x0>;
368 clock-frequency = <54000000>;
372 compatible = "brcm,bcm2711-cprman";
376 coefficients = <(-487) 410040>;
377 thermal-sensors = <&thermal>;
381 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
385 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
389 compatible = "brcm,bcm2711-gpio";
390 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
395 gpclk0_gpio49: gpclk0_gpio49 {
402 gpclk1_gpio50: gpclk1_gpio50 {
409 gpclk2_gpio51: gpclk2_gpio51 {
417 i2c0_gpio46: i2c0_gpio46 {
429 i2c1_gpio46: i2c1_gpio46 {
441 i2c3_gpio2: i2c3_gpio2 {
453 i2c3_gpio4: i2c3_gpio4 {
465 i2c4_gpio6: i2c4_gpio6 {
477 i2c4_gpio8: i2c4_gpio8 {
489 i2c5_gpio10: i2c5_gpio10 {
501 i2c5_gpio12: i2c5_gpio12 {
513 i2c6_gpio0: i2c6_gpio0 {
525 i2c6_gpio22: i2c6_gpio22 {
537 i2c_slave_gpio8: i2c_slave_gpio8 {
547 jtag_gpio48: jtag_gpio48 {
559 mii_gpio28: mii_gpio28 {
568 mii_gpio36: mii_gpio36 {
578 pcm_gpio50: pcm_gpio50 {
588 pwm0_0_gpio12: pwm0_0_gpio12 {
595 pwm0_0_gpio18: pwm0_0_gpio18 {
602 pwm1_0_gpio40: pwm1_0_gpio40 {
609 pwm0_1_gpio13: pwm0_1_gpio13 {
616 pwm0_1_gpio19: pwm0_1_gpio19 {
623 pwm1_1_gpio41: pwm1_1_gpio41 {
630 pwm0_1_gpio45: pwm0_1_gpio45 {
637 pwm0_0_gpio52: pwm0_0_gpio52 {
644 pwm0_1_gpio53: pwm0_1_gpio53 {
652 rgmii_gpio35: rgmii_gpio35 {
662 rgmii_irq_gpio34: rgmii_irq_gpio34 {
668 rgmii_irq_gpio39: rgmii_irq_gpio39 {
674 rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
681 rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
689 spi0_gpio46: spi0_gpio46 {
698 spi2_gpio46: spi2_gpio46 {
708 spi3_gpio0: spi3_gpio0 {
717 spi4_gpio4: spi4_gpio4 {
726 spi5_gpio12: spi5_gpio12 {
735 spi6_gpio18: spi6_gpio18 {
745 uart2_gpio0: uart2_gpio0 {
757 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
769 uart3_gpio4: uart3_gpio4 {
781 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
793 uart4_gpio8: uart4_gpio8 {
805 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
817 uart5_gpio12: uart5_gpio12 {
829 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
844 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
845 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
849 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
850 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
854 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
858 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
862 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
866 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
870 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
874 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
878 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
879 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
880 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
881 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
885 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
889 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
893 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
897 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
901 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;