1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clk/ti-dra7-atl.h>
12 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
22 evm_12v0: fixedregulator-evm12v0 {
24 compatible = "regulator-fixed";
25 regulator-name = "evm_12v0";
26 regulator-min-microvolt = <12000000>;
27 regulator-max-microvolt = <12000000>;
32 evm_5v0: fixedregulator-evm5v0 {
33 /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
34 /* Output 1 of LM5140QRWGTQ1 on dra71-evm */
35 compatible = "regulator-fixed";
36 regulator-name = "evm_5v0";
37 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <5000000>;
39 vin-supply = <&evm_12v0>;
44 evm_3v6: fixedregulator-evm_3v6 {
45 compatible = "regulator-fixed";
46 regulator-name = "evm_3v6";
47 regulator-min-microvolt = <3600000>;
48 regulator-max-microvolt = <3600000>;
49 vin-supply = <&evm_5v0>;
54 vsys_3v3: fixedregulator-vsys3v3 {
55 /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
56 /* Output 2 of LM5140QRWGTQ1 on dra71-evm */
57 compatible = "regulator-fixed";
58 regulator-name = "vsys_3v3";
59 regulator-min-microvolt = <3300000>;
60 regulator-max-microvolt = <3300000>;
61 vin-supply = <&evm_12v0>;
66 evm_3v3_sw: fixedregulator-evm_3v3 {
68 compatible = "regulator-fixed";
69 regulator-name = "evm_3v3";
70 regulator-min-microvolt = <3300000>;
71 regulator-max-microvolt = <3300000>;
72 vin-supply = <&vsys_3v3>;
77 aic_dvdd: fixedregulator-aic_dvdd {
79 compatible = "regulator-fixed";
80 regulator-name = "aic_dvdd";
81 vin-supply = <&evm_3v3_sw>;
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <1800000>;
86 evm_3v3_sd: fixedregulator-sd {
87 compatible = "regulator-fixed";
88 regulator-name = "evm_3v3_sd";
89 regulator-min-microvolt = <3300000>;
90 regulator-max-microvolt = <3300000>;
91 vin-supply = <&evm_3v3_sw>;
93 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
96 extcon_usb1: extcon_usb1 {
97 compatible = "linux,extcon-usb-gpio";
98 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
101 extcon_usb2: extcon_usb2 {
102 compatible = "linux,extcon-usb-gpio";
103 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
107 compatible = "hdmi-connector";
113 hdmi_connector_in: endpoint {
114 remote-endpoint = <&tpd12s015_out>;
120 compatible = "ti,tpd12s015";
122 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
123 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
124 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
127 #address-cells = <1>;
133 tpd12s015_in: endpoint {
134 remote-endpoint = <&hdmi_out>;
141 tpd12s015_out: endpoint {
142 remote-endpoint = <&hdmi_connector_in>;
149 compatible = "simple-audio-card";
150 simple-audio-card,name = "DRA7xx-EVM";
151 simple-audio-card,widgets =
152 "Headphone", "Headphone Jack",
154 "Microphone", "Mic Jack",
156 simple-audio-card,routing =
157 "Headphone Jack", "HPLOUT",
158 "Headphone Jack", "HPROUT",
163 "Mic Jack", "Mic Bias",
166 simple-audio-card,format = "dsp_b";
167 simple-audio-card,bitclock-master = <&sound0_master>;
168 simple-audio-card,frame-master = <&sound0_master>;
169 simple-audio-card,bitclock-inversion;
171 sound0_master: simple-audio-card,cpu {
172 sound-dai = <&mcasp3>;
173 system-clock-frequency = <5644800>;
176 simple-audio-card,codec {
177 sound-dai = <&tlv320aic3106>;
178 clocks = <&atl_clkin2_ck>;
182 vmmcwl_fixed: fixedregulator-mmcwl {
183 compatible = "regulator-fixed";
184 regulator-name = "vmmcwl_fixed";
185 regulator-min-microvolt = <1800000>;
186 regulator-max-microvolt = <1800000>;
187 gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
193 dcan1_pins_default: dcan1_pins_default {
194 pinctrl-single,pins = <
195 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
196 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
200 dcan1_pins_sleep: dcan1_pins_sleep {
201 pinctrl-single,pins = <
202 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
203 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
210 clock-frequency = <400000>;
213 compatible = "nxp,pcf8575";
217 interrupt-controller;
218 #interrupt-cells = <2>;
221 pcf_gpio_21: gpio@21 {
222 compatible = "ti,pcf8575", "nxp,pcf8575";
224 lines-initial-states = <0x1408>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
231 tlv320aic3106: tlv320aic3106@19 {
232 #sound-dai-cells = <0>;
233 compatible = "ti,tlv320aic3106";
235 adc-settle-ms = <40>;
236 ai3x-micbias-vg = <1>; /* 2.0V */
240 AVDD-supply = <&evm_3v3_sw>;
241 IOVDD-supply = <&evm_3v3_sw>;
242 DRVDD-supply = <&evm_3v3_sw>;
243 DVDD-supply = <&aic_dvdd>;
249 clock-frequency = <400000>;
251 pcf_hdmi: pcf8575@26 {
252 compatible = "ti,pcf8575", "nxp,pcf8575";
257 * initial state is used here to keep the mdio interface
258 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
259 * VIN2_S0 driven high otherwise Ethernet stops working
260 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
262 lines-initial-states = <0x0f2b>;
265 /* vin6_sel_s0: high: VIN6, low: audio */
267 gpios = <1 GPIO_ACTIVE_HIGH>;
269 line-name = "vin6_sel_s0";
276 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
277 <&dra7_pmx_core 0x3e0>;
286 * For the existing IOdelay configuration via U-Boot we don't
287 * support NAND on dra72-evm. Keep it disabled. Enabling it
288 * requires a different configuration by U-Boot.
291 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
293 /* To use NAND, DIP switch SW5 must be set like so:
294 * SW5.1 (NAND_SELn) = ON (LOW)
295 * SW5.9 (GPMC_WPN) = OFF (HIGH)
297 compatible = "ti,omap2-nand";
298 reg = <0 0 4>; /* device IO registers */
299 interrupt-parent = <&gpmc>;
300 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
301 <1 IRQ_TYPE_NONE>; /* termcount */
302 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
303 ti,nand-xfer-type = "prefetch-dma";
304 ti,nand-ecc-opt = "bch8";
306 nand-bus-width = <16>;
307 gpmc,device-width = <2>;
308 gpmc,sync-clk-ps = <0>;
310 gpmc,cs-rd-off-ns = <80>;
311 gpmc,cs-wr-off-ns = <80>;
312 gpmc,adv-on-ns = <0>;
313 gpmc,adv-rd-off-ns = <60>;
314 gpmc,adv-wr-off-ns = <60>;
315 gpmc,we-on-ns = <10>;
316 gpmc,we-off-ns = <50>;
318 gpmc,oe-off-ns = <40>;
319 gpmc,access-ns = <40>;
320 gpmc,wr-access-ns = <80>;
321 gpmc,rd-cycle-ns = <80>;
322 gpmc,wr-cycle-ns = <80>;
323 gpmc,bus-turnaround-ns = <0>;
324 gpmc,cycle2cycle-delay-ns = <0>;
325 gpmc,clk-activation-ns = <0>;
326 gpmc,wr-data-mux-bus-ns = <0>;
327 /* MTD partition table */
328 /* All SPL-* partitions are sized to minimal length
329 * which can be independently programmable. For
330 * NAND flash this is equal to size of erase-block */
331 #address-cells = <1>;
335 reg = <0x00000000 0x000020000>;
338 label = "NAND.SPL.backup1";
339 reg = <0x00020000 0x00020000>;
342 label = "NAND.SPL.backup2";
343 reg = <0x00040000 0x00020000>;
346 label = "NAND.SPL.backup3";
347 reg = <0x00060000 0x00020000>;
350 label = "NAND.u-boot-spl-os";
351 reg = <0x00080000 0x00040000>;
354 label = "NAND.u-boot";
355 reg = <0x000c0000 0x00100000>;
358 label = "NAND.u-boot-env";
359 reg = <0x001c0000 0x00020000>;
362 label = "NAND.u-boot-env.backup1";
363 reg = <0x001e0000 0x00020000>;
366 label = "NAND.kernel";
367 reg = <0x00200000 0x00800000>;
370 label = "NAND.file-system";
371 reg = <0x00a00000 0x0f600000>;
377 extcon = <&extcon_usb1>;
381 extcon = <&extcon_usb2>;
386 extcon = <&extcon_usb1>;
391 extcon = <&extcon_usb2>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&mmc1_pins_default>;
398 vmmc-supply = <&evm_3v3_sd>;
401 * SDCD signal is not being used here - using the fact that GPIO mode
402 * is a viable alternative
404 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
405 max-frequency = <192000000>;
409 /* SW5-3 in ON position */
411 pinctrl-names = "default";
412 pinctrl-0 = <&mmc2_pins_default>;
415 max-frequency = <192000000>;
420 vmmc-supply = <&evm_3v6>;
421 vqmmc-supply = <&vmmcwl_fixed>;
424 keep-power-in-suspend;
426 pinctrl-names = "default", "hs", "sdr12", "sdr25";
427 pinctrl-0 = <&mmc4_pins_default>;
428 pinctrl-1 = <&mmc4_pins_default>;
429 pinctrl-2 = <&mmc4_pins_default>;
430 pinctrl-3 = <&mmc4_pins_default>;
431 #address-cells = <1>;
434 compatible = "ti,wl1835";
436 interrupt-parent = <&gpio5>;
437 interrupts = <7 IRQ_TYPE_EDGE_RISING>;
447 pinctrl-names = "default", "sleep", "active";
448 pinctrl-0 = <&dcan1_pins_sleep>;
449 pinctrl-1 = <&dcan1_pins_sleep>;
450 pinctrl-2 = <&dcan1_pins_default>;
456 spi-max-frequency = <76800000>;
458 compatible = "s25fl256s1";
459 spi-max-frequency = <76800000>;
461 spi-tx-bus-width = <1>;
462 spi-rx-bus-width = <4>;
463 #address-cells = <1>;
466 /* MTD partition table.
467 * The ROM checks the first four physical blocks
468 * for a valid file to boot and the flash here is
473 reg = <0x00000000 0x000010000>;
476 label = "QSPI.SPL.backup1";
477 reg = <0x00010000 0x00010000>;
480 label = "QSPI.SPL.backup2";
481 reg = <0x00020000 0x00010000>;
484 label = "QSPI.SPL.backup3";
485 reg = <0x00030000 0x00010000>;
488 label = "QSPI.u-boot";
489 reg = <0x00040000 0x00100000>;
492 label = "QSPI.u-boot-spl-os";
493 reg = <0x00140000 0x00080000>;
496 label = "QSPI.u-boot-env";
497 reg = <0x001c0000 0x00010000>;
500 label = "QSPI.u-boot-env.backup1";
501 reg = <0x001d0000 0x0010000>;
504 label = "QSPI.kernel";
505 reg = <0x001e0000 0x0800000>;
508 label = "QSPI.file-system";
509 reg = <0x009e0000 0x01620000>;
523 remote-endpoint = <&tpd12s015_in>;
529 assigned-clocks = <&abe_dpll_sys_clk_mux>,
530 <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>,
534 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
535 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
540 bws = <DRA7_ATL_WS_MCASP2_FSX>;
541 aws = <DRA7_ATL_WS_MCASP3_FSX>;
546 #sound-dai-cells = <0>;
548 assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
549 assigned-clock-parents = <&atl_clkin2_ck>;
553 op-mode = <0>; /* MCASP_IIS_MODE */
556 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
565 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
568 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
575 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {