| blob | b016b0b683064bc1d51f44a7b6ca41bd13cf1ebf |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos3250 SoC device tree source
4 *
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
9 * based board files can include this file and provide values for board specfic
10 * bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
14 * nodes can be added to this file.
15 */
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
22 / {
23 compatible = "samsung,exynos3250";
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
28 aliases {
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 mshc0 = &mshc_0;
32 mshc1 = &mshc_1;
33 mshc2 = &mshc_2;
34 spi0 = &spi_0;
35 spi1 = &spi_1;
36 i2c0 = &i2c_0;
37 i2c1 = &i2c_1;
38 i2c2 = &i2c_2;
39 i2c3 = &i2c_3;
40 i2c4 = &i2c_4;
41 i2c5 = &i2c_5;
42 i2c6 = &i2c_6;
43 i2c7 = &i2c_7;
44 serial0 = &serial_0;
45 serial1 = &serial_1;
46 serial2 = &serial_2;
47 };
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a7";
56 reg = <0>;
57 clock-frequency = <1000000000>;
58 clocks = <&cmu CLK_ARM_CLK>;
59 clock-names = "cpu";
60 #cooling-cells = <2>;
62 operating-points = <
63 1000000 1150000
64 900000 1112500
65 800000 1075000
66 700000 1037500
67 600000 1000000
68 500000 962500
69 400000 925000
70 300000 887500
71 200000 850000
72 100000 850000
73 >;
74 };
76 cpu1: cpu@1 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a7";
79 reg = <1>;
80 clock-frequency = <1000000000>;
81 clocks = <&cmu CLK_ARM_CLK>;
82 clock-names = "cpu";
83 #cooling-cells = <2>;
85 operating-points = <
86 1000000 1150000
87 900000 1112500
88 800000 1075000
89 700000 1037500
90 600000 1000000
91 500000 962500
92 400000 925000
93 300000 887500
94 200000 850000
95 100000 850000
96 >;
97 };
98 };
100 fixed-rate-clocks {
101 #address-cells = <1>;
102 #size-cells = <0>;
104 xusbxti: clock@0 {
105 compatible = "fixed-clock";
106 reg = <0>;
107 clock-frequency = <0>;
108 #clock-cells = <0>;
109 clock-output-names = "xusbxti";
110 };
112 xxti: clock@1 {
113 compatible = "fixed-clock";
114 reg = <1>;
115 clock-frequency = <0>;
116 #clock-cells = <0>;
117 clock-output-names = "xxti";
118 };
120 xtcxo: clock@2 {
121 compatible = "fixed-clock";
122 reg = <2>;
123 clock-frequency = <0>;
124 #clock-cells = <0>;
125 clock-output-names = "xtcxo";
126 };
127 };
129 pmu {
130 compatible = "arm,cortex-a7-pmu";
131 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
133 };
135 soc: soc {
136 compatible = "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges;
141 sram@2020000 {
142 compatible = "mmio-sram";
143 reg = <0x02020000 0x40000>;
144 #address-cells = <1>;
145 #size-cells = <1>;
146 ranges = <0 0x02020000 0x40000>;
148 smp-sysram@0 {
149 compatible = "samsung,exynos4210-sysram";
150 reg = <0x0 0x1000>;
151 };
153 smp-sysram@3f000 {
154 compatible = "samsung,exynos4210-sysram-ns";
155 reg = <0x3f000 0x1000>;
156 };
157 };
159 chipid@10000000 {
160 compatible = "samsung,exynos4210-chipid";
161 reg = <0x10000000 0x100>;
162 };
164 sys_reg: syscon@10010000 {
165 compatible = "samsung,exynos3-sysreg", "syscon";
166 reg = <0x10010000 0x400>;
167 };
169 pmu_system_controller: system-controller@10020000 {
170 compatible = "samsung,exynos3250-pmu", "syscon";
171 reg = <0x10020000 0x4000>;
172 interrupt-controller;
173 #interrupt-cells = <3>;
174 interrupt-parent = <&gic>;
175 clock-names = "clkout8";
176 clocks = <&cmu CLK_FIN_PLL>;
177 #clock-cells = <1>;
178 };
180 mipi_phy: video-phy {
181 compatible = "samsung,s5pv210-mipi-video-phy";
182 #phy-cells = <1>;
183 syscon = <&pmu_system_controller>;
184 };
186 pd_cam: power-domain@10023c00 {
187 compatible = "samsung,exynos4210-pd";
188 reg = <0x10023C00 0x20>;
189 #power-domain-cells = <0>;
190 label = "CAM";
191 };
193 pd_mfc: power-domain@10023c40 {
194 compatible = "samsung,exynos4210-pd";
195 reg = <0x10023C40 0x20>;
196 #power-domain-cells = <0>;
197 label = "MFC";
198 };
200 pd_g3d: power-domain@10023c60 {
201 compatible = "samsung,exynos4210-pd";
202 reg = <0x10023C60 0x20>;
203 #power-domain-cells = <0>;
204 label = "G3D";
205 };
207 pd_lcd0: power-domain@10023c80 {
208 compatible = "samsung,exynos4210-pd";
209 reg = <0x10023C80 0x20>;
210 #power-domain-cells = <0>;
211 label = "LCD0";
212 };
214 pd_isp: power-domain@10023ca0 {
215 compatible = "samsung,exynos4210-pd";
216 reg = <0x10023CA0 0x20>;
217 #power-domain-cells = <0>;
218 label = "ISP";
219 };
221 cmu: clock-controller@10030000 {
222 compatible = "samsung,exynos3250-cmu";
223 reg = <0x10030000 0x20000>;
224 #clock-cells = <1>;
225 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
226 <&cmu CLK_MOUT_ACLK_266_SUB>;
227 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
228 <&cmu CLK_FIN_PLL>;
229 };
231 cmu_dmc: clock-controller@105c0000 {
232 compatible = "samsung,exynos3250-cmu-dmc";
233 reg = <0x105C0000 0x2000>;
234 #clock-cells = <1>;
235 };
237 rtc: rtc@10070000 {
238 compatible = "samsung,s3c6410-rtc";
239 reg = <0x10070000 0x100>;
240 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
242 interrupt-parent = <&pmu_system_controller>;
243 status = "disabled";
244 };
246 tmu: tmu@100c0000 {
247 compatible = "samsung,exynos3250-tmu";
248 reg = <0x100C0000 0x100>;
249 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&cmu CLK_TMU_APBIF>;
251 clock-names = "tmu_apbif";
252 #thermal-sensor-cells = <0>;
253 status = "disabled";
254 };
256 gic: interrupt-controller@10481000 {
257 compatible = "arm,cortex-a15-gic";
258 #interrupt-cells = <3>;
259 interrupt-controller;
260 reg = <0x10481000 0x1000>,
261 <0x10482000 0x2000>,
262 <0x10484000 0x2000>,
263 <0x10486000 0x2000>;
264 interrupts = <GIC_PPI 9
265 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
266 };
268 timer@10050000 {
269 compatible = "samsung,exynos4210-mct";
270 reg = <0x10050000 0x800>;
271 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
280 clock-names = "fin_pll", "mct";
281 };
283 pinctrl_1: pinctrl@11000000 {
284 compatible = "samsung,exynos3250-pinctrl";
285 reg = <0x11000000 0x1000>;
286 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
288 wakeup-interrupt-controller {
289 compatible = "samsung,exynos4210-wakeup-eint";
290 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
291 };
292 };
294 pinctrl_0: pinctrl@11400000 {
295 compatible = "samsung,exynos3250-pinctrl";
296 reg = <0x11400000 0x1000>;
297 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
298 };
300 jpeg: codec@11830000 {
301 compatible = "samsung,exynos3250-jpeg";
302 reg = <0x11830000 0x1000>;
303 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
305 clock-names = "jpeg", "sclk";
306 power-domains = <&pd_cam>;
307 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
308 assigned-clock-rates = <0>, <150000000>;
309 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
310 iommus = <&sysmmu_jpeg>;
311 status = "disabled";
312 };
314 sysmmu_jpeg: sysmmu@11a60000 {
315 compatible = "samsung,exynos-sysmmu";
316 reg = <0x11a60000 0x1000>;
317 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
318 clock-names = "sysmmu", "master";
319 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
320 power-domains = <&pd_cam>;
321 #iommu-cells = <0>;
322 };
324 fimd: fimd@11c00000 {
325 compatible = "samsung,exynos3250-fimd";
326 reg = <0x11c00000 0x30000>;
327 interrupt-names = "fifo", "vsync", "lcd_sys";
328 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
332 clock-names = "sclk_fimd", "fimd";
333 power-domains = <&pd_lcd0>;
334 iommus = <&sysmmu_fimd0>;
335 samsung,sysreg = <&sys_reg>;
336 status = "disabled";
337 };
339 dsi_0: dsi@11c80000 {
340 compatible = "samsung,exynos3250-mipi-dsi";
341 reg = <0x11C80000 0x10000>;
342 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
343 samsung,phy-type = <0>;
344 power-domains = <&pd_lcd0>;
345 phys = <&mipi_phy 1>;
346 phy-names = "dsim";
347 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
348 clock-names = "bus_clk", "pll_clk";
349 #address-cells = <1>;
350 #size-cells = <0>;
351 status = "disabled";
352 };
354 sysmmu_fimd0: sysmmu@11e20000 {
355 compatible = "samsung,exynos-sysmmu";
356 reg = <0x11e20000 0x1000>;
357 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
358 clock-names = "sysmmu", "master";
359 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
360 power-domains = <&pd_lcd0>;
361 #iommu-cells = <0>;
362 };
364 hsotg: hsotg@12480000 {
365 compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
366 reg = <0x12480000 0x20000>;
367 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&cmu CLK_USBOTG>;
369 clock-names = "otg";
370 phys = <&exynos_usbphy 0>;
371 phy-names = "usb2-phy";
372 status = "disabled";
373 };
375 mshc_0: mshc@12510000 {
376 compatible = "samsung,exynos5420-dw-mshc";
377 reg = <0x12510000 0x1000>;
378 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
380 clock-names = "biu", "ciu";
381 fifo-depth = <0x80>;
382 #address-cells = <1>;
383 #size-cells = <0>;
384 status = "disabled";
385 };
387 mshc_1: mshc@12520000 {
388 compatible = "samsung,exynos5420-dw-mshc";
389 reg = <0x12520000 0x1000>;
390 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
392 clock-names = "biu", "ciu";
393 fifo-depth = <0x80>;
394 #address-cells = <1>;
395 #size-cells = <0>;
396 status = "disabled";
397 };
399 mshc_2: mshc@12530000 {
400 compatible = "samsung,exynos5250-dw-mshc";
401 reg = <0x12530000 0x1000>;
402 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
404 clock-names = "biu", "ciu";
405 fifo-depth = <0x80>;
406 #address-cells = <1>;
407 #size-cells = <0>;
408 status = "disabled";
409 };
411 exynos_usbphy: exynos-usbphy@125b0000 {
412 compatible = "samsung,exynos3250-usb2-phy";
413 reg = <0x125B0000 0x100>;
414 samsung,pmureg-phandle = <&pmu_system_controller>;
415 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
416 clock-names = "phy", "ref";
417 #phy-cells = <1>;
418 status = "disabled";
419 };
421 amba {
422 compatible = "simple-bus";
423 #address-cells = <1>;
424 #size-cells = <1>;
425 ranges;
427 pdma0: pdma@12680000 {
428 compatible = "arm,pl330", "arm,primecell";
429 reg = <0x12680000 0x1000>;
430 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&cmu CLK_PDMA0>;
432 clock-names = "apb_pclk";
433 #dma-cells = <1>;
434 #dma-channels = <8>;
435 #dma-requests = <32>;
436 };
438 pdma1: pdma@12690000 {
439 compatible = "arm,pl330", "arm,primecell";
440 reg = <0x12690000 0x1000>;
441 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&cmu CLK_PDMA1>;
443 clock-names = "apb_pclk";
444 #dma-cells = <1>;
445 #dma-channels = <8>;
446 #dma-requests = <32>;
447 };
448 };
450 adc: adc@126c0000 {
451 compatible = "samsung,exynos3250-adc";
452 reg = <0x126C0000 0x100>;
453 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
454 clock-names = "adc", "sclk";
455 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
456 #io-channel-cells = <1>;
457 io-channel-ranges;
458 samsung,syscon-phandle = <&pmu_system_controller>;
459 status = "disabled";
460 };
462 gpu: gpu@13000000 {
463 compatible = "samsung,exynos4210-mali", "arm,mali-400";
464 reg = <0x13000000 0x10000>;
465 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-names = "gp",
477 "gpmmu",
478 "pp0",
479 "ppmmu0",
480 "pp1",
481 "ppmmu1",
482 "pp2",
483 "ppmmu2",
484 "pp3",
485 "ppmmu3",
486 "pmu";
487 clocks = <&cmu CLK_G3D>,
488 <&cmu CLK_SCLK_G3D>;
489 clock-names = "bus", "core";
490 power-domains = <&pd_g3d>;
491 status = "disabled";
492 /* TODO: operating points for DVFS, assigned clock as 134 MHz */
493 };
495 mfc: codec@13400000 {
496 compatible = "samsung,mfc-v7";
497 reg = <0x13400000 0x10000>;
498 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
499 clock-names = "mfc", "sclk_mfc";
500 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
501 power-domains = <&pd_mfc>;
502 iommus = <&sysmmu_mfc>;
503 };
505 sysmmu_mfc: sysmmu@13620000 {
506 compatible = "samsung,exynos-sysmmu";
507 reg = <0x13620000 0x1000>;
508 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
509 clock-names = "sysmmu", "master";
510 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
511 power-domains = <&pd_mfc>;
512 #iommu-cells = <0>;
513 };
515 serial_0: serial@13800000 {
516 compatible = "samsung,exynos4210-uart";
517 reg = <0x13800000 0x100>;
518 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
520 clock-names = "uart", "clk_uart_baud0";
521 pinctrl-names = "default";
522 pinctrl-0 = <&uart0_data &uart0_fctl>;
523 status = "disabled";
524 };
526 serial_1: serial@13810000 {
527 compatible = "samsung,exynos4210-uart";
528 reg = <0x13810000 0x100>;
529 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
531 clock-names = "uart", "clk_uart_baud0";
532 pinctrl-names = "default";
533 pinctrl-0 = <&uart1_data>;
534 status = "disabled";
535 };
537 serial_2: serial@13820000 {
538 compatible = "samsung,exynos4210-uart";
539 reg = <0x13820000 0x100>;
540 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
542 clock-names = "uart", "clk_uart_baud0";
543 pinctrl-names = "default";
544 pinctrl-0 = <&uart2_data>;
545 status = "disabled";
546 };
548 i2c_0: i2c@13860000 {
549 #address-cells = <1>;
550 #size-cells = <0>;
551 compatible = "samsung,s3c2440-i2c";
552 reg = <0x13860000 0x100>;
553 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&cmu CLK_I2C0>;
555 clock-names = "i2c";
556 pinctrl-names = "default";
557 pinctrl-0 = <&i2c0_bus>;
558 status = "disabled";
559 };
561 i2c_1: i2c@13870000 {
562 #address-cells = <1>;
563 #size-cells = <0>;
564 compatible = "samsung,s3c2440-i2c";
565 reg = <0x13870000 0x100>;
566 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&cmu CLK_I2C1>;
568 clock-names = "i2c";
569 pinctrl-names = "default";
570 pinctrl-0 = <&i2c1_bus>;
571 status = "disabled";
572 };
574 i2c_2: i2c@13880000 {
575 #address-cells = <1>;
576 #size-cells = <0>;
577 compatible = "samsung,s3c2440-i2c";
578 reg = <0x13880000 0x100>;
579 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&cmu CLK_I2C2>;
581 clock-names = "i2c";
582 pinctrl-names = "default";
583 pinctrl-0 = <&i2c2_bus>;
584 status = "disabled";
585 };
587 i2c_3: i2c@13890000 {
588 #address-cells = <1>;
589 #size-cells = <0>;
590 compatible = "samsung,s3c2440-i2c";
591 reg = <0x13890000 0x100>;
592 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&cmu CLK_I2C3>;
594 clock-names = "i2c";
595 pinctrl-names = "default";
596 pinctrl-0 = <&i2c3_bus>;
597 status = "disabled";
598 };
600 i2c_4: i2c@138a0000 {
601 #address-cells = <1>;
602 #size-cells = <0>;
603 compatible = "samsung,s3c2440-i2c";
604 reg = <0x138A0000 0x100>;
605 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&cmu CLK_I2C4>;
607 clock-names = "i2c";
608 pinctrl-names = "default";
609 pinctrl-0 = <&i2c4_bus>;
610 status = "disabled";
611 };
613 i2c_5: i2c@138b0000 {
614 #address-cells = <1>;
615 #size-cells = <0>;
616 compatible = "samsung,s3c2440-i2c";
617 reg = <0x138B0000 0x100>;
618 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cmu CLK_I2C5>;
620 clock-names = "i2c";
621 pinctrl-names = "default";
622 pinctrl-0 = <&i2c5_bus>;
623 status = "disabled";
624 };
626 i2c_6: i2c@138c0000 {
627 #address-cells = <1>;
628 #size-cells = <0>;
629 compatible = "samsung,s3c2440-i2c";
630 reg = <0x138C0000 0x100>;
631 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&cmu CLK_I2C6>;
633 clock-names = "i2c";
634 pinctrl-names = "default";
635 pinctrl-0 = <&i2c6_bus>;
636 status = "disabled";
637 };
639 i2c_7: i2c@138d0000 {
640 #address-cells = <1>;
641 #size-cells = <0>;
642 compatible = "samsung,s3c2440-i2c";
643 reg = <0x138D0000 0x100>;
644 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&cmu CLK_I2C7>;
646 clock-names = "i2c";
647 pinctrl-names = "default";
648 pinctrl-0 = <&i2c7_bus>;
649 status = "disabled";
650 };
652 spi_0: spi@13920000 {
653 compatible = "samsung,exynos4210-spi";
654 reg = <0x13920000 0x100>;
655 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
656 dmas = <&pdma0 7>, <&pdma0 6>;
657 dma-names = "tx", "rx";
658 #address-cells = <1>;
659 #size-cells = <0>;
660 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
661 clock-names = "spi", "spi_busclk0";
662 samsung,spi-src-clk = <0>;
663 pinctrl-names = "default";
664 pinctrl-0 = <&spi0_bus>;
665 status = "disabled";
666 };
668 spi_1: spi@13930000 {
669 compatible = "samsung,exynos4210-spi";
670 reg = <0x13930000 0x100>;
671 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
672 dmas = <&pdma1 7>, <&pdma1 6>;
673 dma-names = "tx", "rx";
674 #address-cells = <1>;
675 #size-cells = <0>;
676 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
677 clock-names = "spi", "spi_busclk0";
678 samsung,spi-src-clk = <0>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&spi1_bus>;
681 status = "disabled";
682 };
684 i2s2: i2s@13970000 {
685 compatible = "samsung,s3c6410-i2s";
686 reg = <0x13970000 0x100>;
687 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
689 clock-names = "iis", "i2s_opclk0";
690 dmas = <&pdma0 14>, <&pdma0 13>;
691 dma-names = "tx", "rx";
692 pinctrl-0 = <&i2s2_bus>;
693 pinctrl-names = "default";
694 status = "disabled";
695 };
697 pwm: pwm@139d0000 {
698 compatible = "samsung,exynos4210-pwm";
699 reg = <0x139D0000 0x1000>;
700 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
705 #pwm-cells = <3>;
706 status = "disabled";
707 };
709 ppmu_dmc0: ppmu_dmc0@106a0000 {
710 compatible = "samsung,exynos-ppmu";
711 reg = <0x106a0000 0x2000>;
712 status = "disabled";
713 };
715 ppmu_dmc1: ppmu_dmc1@106b0000 {
716 compatible = "samsung,exynos-ppmu";
717 reg = <0x106b0000 0x2000>;
718 status = "disabled";
719 };
721 ppmu_cpu: ppmu_cpu@106c0000 {
722 compatible = "samsung,exynos-ppmu";
723 reg = <0x106c0000 0x2000>;
724 status = "disabled";
725 };
727 ppmu_rightbus: ppmu_rightbus@112a0000 {
728 compatible = "samsung,exynos-ppmu";
729 reg = <0x112a0000 0x2000>;
730 clocks = <&cmu CLK_PPMURIGHT>;
731 clock-names = "ppmu";
732 status = "disabled";
733 };
735 ppmu_leftbus: ppmu_leftbus0@116a0000 {
736 compatible = "samsung,exynos-ppmu";
737 reg = <0x116a0000 0x2000>;
738 clocks = <&cmu CLK_PPMULEFT>;
739 clock-names = "ppmu";
740 status = "disabled";
741 };
743 ppmu_camif: ppmu_camif@11ac0000 {
744 compatible = "samsung,exynos-ppmu";
745 reg = <0x11ac0000 0x2000>;
746 clocks = <&cmu CLK_PPMUCAMIF>;
747 clock-names = "ppmu";
748 status = "disabled";
749 };
751 ppmu_lcd0: ppmu_lcd0@11e40000 {
752 compatible = "samsung,exynos-ppmu";
753 reg = <0x11e40000 0x2000>;
754 clocks = <&cmu CLK_PPMULCD0>;
755 clock-names = "ppmu";
756 status = "disabled";
757 };
759 ppmu_fsys: ppmu_fsys@12630000 {
760 compatible = "samsung,exynos-ppmu";
761 reg = <0x12630000 0x2000>;
762 clocks = <&cmu CLK_PPMUFILE>;
763 clock-names = "ppmu";
764 status = "disabled";
765 };
767 ppmu_g3d: ppmu_g3d@13220000 {
768 compatible = "samsung,exynos-ppmu";
769 reg = <0x13220000 0x2000>;
770 clocks = <&cmu CLK_PPMUG3D>;
771 clock-names = "ppmu";
772 status = "disabled";
773 };
775 ppmu_mfc: ppmu_mfc@13660000 {
776 compatible = "samsung,exynos-ppmu";
777 reg = <0x13660000 0x2000>;
778 clocks = <&cmu CLK_PPMUMFC_L>;
779 clock-names = "ppmu";
780 status = "disabled";
781 };
783 bus_dmc: bus_dmc {
784 compatible = "samsung,exynos-bus";
785 clocks = <&cmu_dmc CLK_DIV_DMC>;
786 clock-names = "bus";
787 operating-points-v2 = <&bus_dmc_opp_table>;
788 status = "disabled";
789 };
791 bus_dmc_opp_table: opp_table1 {
792 compatible = "operating-points-v2";
793 opp-shared;
795 opp-50000000 {
796 opp-hz = /bits/ 64 <50000000>;
797 opp-microvolt = <800000>;
798 };
799 opp-100000000 {
800 opp-hz = /bits/ 64 <100000000>;
801 opp-microvolt = <800000>;
802 };
803 opp-134000000 {
804 opp-hz = /bits/ 64 <134000000>;
805 opp-microvolt = <800000>;
806 };
807 opp-200000000 {
808 opp-hz = /bits/ 64 <200000000>;
809 opp-microvolt = <825000>;
810 };
811 opp-400000000 {
812 opp-hz = /bits/ 64 <400000000>;
813 opp-microvolt = <875000>;
814 };
815 };
817 bus_leftbus: bus_leftbus {
818 compatible = "samsung,exynos-bus";
819 clocks = <&cmu CLK_DIV_GDL>;
820 clock-names = "bus";
821 operating-points-v2 = <&bus_leftbus_opp_table>;
822 status = "disabled";
823 };
825 bus_rightbus: bus_rightbus {
826 compatible = "samsung,exynos-bus";
827 clocks = <&cmu CLK_DIV_GDR>;
828 clock-names = "bus";
829 operating-points-v2 = <&bus_leftbus_opp_table>;
830 status = "disabled";
831 };
833 bus_lcd0: bus_lcd0 {
834 compatible = "samsung,exynos-bus";
835 clocks = <&cmu CLK_DIV_ACLK_160>;
836 clock-names = "bus";
837 operating-points-v2 = <&bus_leftbus_opp_table>;
838 status = "disabled";
839 };
841 bus_fsys: bus_fsys {
842 compatible = "samsung,exynos-bus";
843 clocks = <&cmu CLK_DIV_ACLK_200>;
844 clock-names = "bus";
845 operating-points-v2 = <&bus_leftbus_opp_table>;
846 status = "disabled";
847 };
849 bus_mcuisp: bus_mcuisp {
850 compatible = "samsung,exynos-bus";
851 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
852 clock-names = "bus";
853 operating-points-v2 = <&bus_mcuisp_opp_table>;
854 status = "disabled";
855 };
857 bus_isp: bus_isp {
858 compatible = "samsung,exynos-bus";
859 clocks = <&cmu CLK_DIV_ACLK_266>;
860 clock-names = "bus";
861 operating-points-v2 = <&bus_isp_opp_table>;
862 status = "disabled";
863 };
865 bus_peril: bus_peril {
866 compatible = "samsung,exynos-bus";
867 clocks = <&cmu CLK_DIV_ACLK_100>;
868 clock-names = "bus";
869 operating-points-v2 = <&bus_peril_opp_table>;
870 status = "disabled";
871 };
873 bus_mfc: bus_mfc {
874 compatible = "samsung,exynos-bus";
875 clocks = <&cmu CLK_SCLK_MFC>;
876 clock-names = "bus";
877 operating-points-v2 = <&bus_leftbus_opp_table>;
878 status = "disabled";
879 };
881 bus_leftbus_opp_table: opp_table2 {
882 compatible = "operating-points-v2";
883 opp-shared;
885 opp-50000000 {
886 opp-hz = /bits/ 64 <50000000>;
887 opp-microvolt = <900000>;
888 };
889 opp-80000000 {
890 opp-hz = /bits/ 64 <80000000>;
891 opp-microvolt = <900000>;
892 };
893 opp-100000000 {
894 opp-hz = /bits/ 64 <100000000>;
895 opp-microvolt = <1000000>;
896 };
897 opp-134000000 {
898 opp-hz = /bits/ 64 <134000000>;
899 opp-microvolt = <1000000>;
900 };
901 opp-200000000 {
902 opp-hz = /bits/ 64 <200000000>;
903 opp-microvolt = <1000000>;
904 };
905 };
907 bus_mcuisp_opp_table: opp_table3 {
908 compatible = "operating-points-v2";
909 opp-shared;
911 opp-50000000 {
912 opp-hz = /bits/ 64 <50000000>;
913 };
914 opp-80000000 {
915 opp-hz = /bits/ 64 <80000000>;
916 };
917 opp-100000000 {
918 opp-hz = /bits/ 64 <100000000>;
919 };
920 opp-200000000 {
921 opp-hz = /bits/ 64 <200000000>;
922 };
923 opp-400000000 {
924 opp-hz = /bits/ 64 <400000000>;
925 };
926 };
928 bus_isp_opp_table: opp_table4 {
929 compatible = "operating-points-v2";
930 opp-shared;
932 opp-50000000 {
933 opp-hz = /bits/ 64 <50000000>;
934 };
935 opp-80000000 {
936 opp-hz = /bits/ 64 <80000000>;
937 };
938 opp-100000000 {
939 opp-hz = /bits/ 64 <100000000>;
940 };
941 opp-200000000 {
942 opp-hz = /bits/ 64 <200000000>;
943 };
944 opp-300000000 {
945 opp-hz = /bits/ 64 <300000000>;
946 };
947 };
949 bus_peril_opp_table: opp_table5 {
950 compatible = "operating-points-v2";
951 opp-shared;
953 opp-50000000 {
954 opp-hz = /bits/ 64 <50000000>;
955 };
956 opp-80000000 {
957 opp-hz = /bits/ 64 <80000000>;
958 };
959 opp-100000000 {
960 opp-hz = /bits/ 64 <100000000>;
961 };
962 };
963 };
964 };
966 #include "exynos3250-pinctrl.dtsi"
967 #include "exynos-syscon-restart.dtsi"